Commit ea956685 authored by Matt Arsenault's avatar Matt Arsenault Committed by Matt Arsenault
Browse files

GlobalISel: Implement s32->s64 G_FPTOSI lowering 

Port directly from DAG version.

The lowering for G_FPTOUI used to fail on AMDGPU because it uses
G_FPTOSI.
parent b21571f4

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

+1 −0
Original line number Diff line number Diff line
@@ -252,6 +252,7 @@ public: 
  LegalizeResult lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);

  LegalizeResult lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);

  LegalizeResult lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty);

  LegalizeResult lowerFPTOSI(MachineInstr &MI);

  LegalizeResult lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty);

  LegalizeResult lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty);

  LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

+69 −0
Original line number Diff line number Diff line
@@ -2438,6 +2438,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { 
    return lowerSITOFP(MI, TypeIdx, Ty);

  case G_FPTOUI:

    return lowerFPTOUI(MI, TypeIdx, Ty);

  case G_FPTOSI:

    return lowerFPTOSI(MI);

  case G_SMIN:

  case G_SMAX:

  case G_UMIN:
@@ -4315,6 +4317,73 @@ LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { 
  return Legalized;

}



LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) {

  Register Dst = MI.getOperand(0).getReg();

  Register Src = MI.getOperand(1).getReg();

  LLT DstTy = MRI.getType(Dst);

  LLT SrcTy = MRI.getType(Src);

  const LLT S64 = LLT::scalar(64);

  const LLT S32 = LLT::scalar(32);



  // FIXME: Only f32 to i64 conversions are supported.

  if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64)

    return UnableToLegalize;



  // Expand f32 -> i64 conversion

  // This algorithm comes from compiler-rt's implementation of fixsfdi:

  // https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/builtins/fixsfdi.c



  unsigned SrcEltBits = SrcTy.getScalarSizeInBits();



  auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000);

  auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23);



  auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask);

  auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit);



  auto SignMask = MIRBuilder.buildConstant(SrcTy,

                                           APInt::getSignMask(SrcEltBits));

  auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask);

  auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1);

  auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit);

  Sign = MIRBuilder.buildSExt(DstTy, Sign);



  auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF);

  auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask);

  auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000);



  auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K);

  R = MIRBuilder.buildZExt(DstTy, R);



  auto Bias = MIRBuilder.buildConstant(SrcTy, 127);

  auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias);

  auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit);

  auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent);



  auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent);

  auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub);



  const LLT S1 = LLT::scalar(1);

  auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT,

                                    S1, Exponent, ExponentLoBit);



  R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl);



  auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign);

  auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign);



  auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0);



  auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT,

                                          S1, Exponent, ZeroSrcTy);



  auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0);

  MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret);



  MI.eraseFromParent();

  return Legalized;

}



static CmpInst::Predicate minMaxToCompare(unsigned Opc) {

  switch (Opc) {

  case TargetOpcode::G_SMIN:

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

+2 −1
Original line number Diff line number Diff line
@@ -465,7 +465,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, 
    FPToI.minScalar(1, S32);



  FPToI.minScalar(0, S32)

       .scalarize(0);

       .scalarize(0)

       .lower();



  getActionDefinitionsBuilder(G_INTRINSIC_ROUND)

    .scalarize(0)

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir

+212 −0
Original line number Diff line number Diff line
@@ -354,3 +354,215 @@ body: | 
    %1:_(<2 x s64>) = G_FPTOSI %0

    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1

...



---

name: test_fptosi_s32_to_s64

body: |

  bb.0:

    liveins: $vgpr0



    ; SI-LABEL: name: test_fptosi_s32_to_s64

    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2139095040

    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23

    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]

    ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)

    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648

    ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]

    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 31

    ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[AND1]], [[C3]](s32)

    ; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ASHR]](s32)

    ; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8388607

    ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]

    ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8388608

    ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[C5]]

    ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[OR]](s32)

    ; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 127

    ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[C6]]

    ; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C1]]

    ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]

    ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[SUB1]](s32)

    ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)

    ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C1]]

    ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[LSHR1]]

    ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SELECT]], [[SEXT]]

    ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)

    ; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT]](s64)

    ; SI: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]

    ; SI: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]

    ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)

    ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C7]]

    ; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0

    ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[C8]], [[MV]]

    ; SI: $vgpr0_vgpr1 = COPY [[SELECT1]](s64)

    ; VI-LABEL: name: test_fptosi_s32_to_s64

    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2139095040

    ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23

    ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]

    ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)

    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648

    ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]

    ; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 31

    ; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[AND1]], [[C3]](s32)

    ; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ASHR]](s32)

    ; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8388607

    ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]

    ; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8388608

    ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[C5]]

    ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[OR]](s32)

    ; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 127

    ; VI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[C6]]

    ; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C1]]

    ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]

    ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[SUB1]](s32)

    ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)

    ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C1]]

    ; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[LSHR1]]

    ; VI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SELECT]], [[SEXT]]

    ; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)

    ; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT]](s64)

    ; VI: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]

    ; VI: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]

    ; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)

    ; VI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C7]]

    ; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0

    ; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[C8]], [[MV]]

    ; VI: $vgpr0_vgpr1 = COPY [[SELECT1]](s64)

    %0:_(s32) = COPY $vgpr0

    %1:_(s64) = G_FPTOSI %0

    $vgpr0_vgpr1 = COPY %1

...



---

name: test_fptosi_v2s32_to_v2s64

body: |

  bb.0:

    liveins: $vgpr0_vgpr1



    ; SI-LABEL: name: test_fptosi_v2s32_to_v2s64

    ; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1

    ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)

    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2139095040

    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23

    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]

    ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)

    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648

    ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]

    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 31

    ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[AND1]], [[C3]](s32)

    ; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ASHR]](s32)

    ; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8388607

    ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C4]]

    ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8388608

    ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[C5]]

    ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[OR]](s32)

    ; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 127

    ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[C6]]

    ; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C1]]

    ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]

    ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[SUB1]](s32)

    ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)

    ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C1]]

    ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[LSHR1]]

    ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SELECT]], [[SEXT]]

    ; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)

    ; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT]](s64)

    ; SI: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV2]], [[UV4]]

    ; SI: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV3]], [[UV5]], [[USUBO1]]

    ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)

    ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C7]]

    ; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0

    ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[C8]], [[MV]]

    ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]

    ; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)

    ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]

    ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[AND4]], [[C3]](s32)

    ; SI: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[ASHR1]](s32)

    ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C4]]

    ; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[C5]]

    ; SI: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[OR1]](s32)

    ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LSHR2]], [[C6]]

    ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[C1]]

    ; SI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB3]]

    ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[SUB4]](s32)

    ; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT1]], [[SUB5]](s32)

    ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB3]](s32), [[C1]]

    ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL1]], [[LSHR3]]

    ; SI: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[SELECT2]], [[SEXT1]]

    ; SI: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)

    ; SI: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT1]](s64)

    ; SI: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[UV8]]

    ; SI: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[UV9]], [[USUBO3]]

    ; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)

    ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB3]](s32), [[C7]]

    ; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[C8]], [[MV1]]

    ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT1]](s64), [[SELECT3]](s64)

    ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)

    ; VI-LABEL: name: test_fptosi_v2s32_to_v2s64

    ; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1

    ; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)

    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2139095040

    ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23

    ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]

    ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)

    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648

    ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]

    ; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 31

    ; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[AND1]], [[C3]](s32)

    ; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ASHR]](s32)

    ; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8388607

    ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C4]]

    ; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8388608

    ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[C5]]

    ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[OR]](s32)

    ; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 127

    ; VI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[C6]]

    ; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[C1]]

    ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]

    ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[SUB1]](s32)

    ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)

    ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C1]]

    ; VI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[SHL]], [[LSHR1]]

    ; VI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SELECT]], [[SEXT]]

    ; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)

    ; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT]](s64)

    ; VI: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV2]], [[UV4]]

    ; VI: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV3]], [[UV5]], [[USUBO1]]

    ; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)

    ; VI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C7]]

    ; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 0

    ; VI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[C8]], [[MV]]

    ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]

    ; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)

    ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]

    ; VI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[AND4]], [[C3]](s32)

    ; VI: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[ASHR1]](s32)

    ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C4]]

    ; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[C5]]

    ; VI: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[OR1]](s32)

    ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LSHR2]], [[C6]]

    ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[C1]]

    ; VI: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB3]]

    ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[SUB4]](s32)

    ; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT1]], [[SUB5]](s32)

    ; VI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB3]](s32), [[C1]]

    ; VI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[SHL1]], [[LSHR3]]

    ; VI: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[SELECT2]], [[SEXT1]]

    ; VI: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)

    ; VI: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT1]](s64)

    ; VI: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[UV8]]

    ; VI: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[UV9]], [[USUBO3]]

    ; VI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)

    ; VI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB3]](s32), [[C7]]

    ; VI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[C8]], [[MV1]]

    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT1]](s64), [[SELECT3]](s64)

    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)

    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1

    %1:_(<2 x s64>) = G_FPTOSI %0

    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1

...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir

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