Commit b21571f4 authored by Matt Arsenault's avatar Matt Arsenault Committed by Matt Arsenault
Browse files

AMDGPU/GlobalISel: Handle s64->s64 G_FPTOSI/G_FPTOUI

parent f9f0919d

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

+6 −0
Original line number Diff line number Diff line
@@ -1420,6 +1420,12 @@ public: 
    return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);

  }



  /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1

  MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0,

                                          Optional<unsigned> Flags = None) {

    return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);

  }



  /// Build and insert \p Dst = G_FLOG \p Src

  MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src,

                                Optional<unsigned> Flags = None) {

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

+42 −1
Original line number Diff line number Diff line
@@ -457,7 +457,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, 
       .scalarize(0);



  auto &FPToI = getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})

    .legalFor({{S32, S32}, {S32, S64}, {S32, S16}});

    .legalFor({{S32, S32}, {S32, S64}, {S32, S16}})

    .customFor({{S64, S64}});

  if (ST.has16BitInsts())

    FPToI.legalFor({{S16, S16}});

  else
@@ -1161,6 +1162,10 @@ bool AMDGPULegalizerInfo::legalizeCustom(MachineInstr &MI, 
    return legalizeITOFP(MI, MRI, B, true);

  case TargetOpcode::G_UITOFP:

    return legalizeITOFP(MI, MRI, B, false);

  case TargetOpcode::G_FPTOSI:

    return legalizeFPTOI(MI, MRI, B, true);

  case TargetOpcode::G_FPTOUI:

    return legalizeFPTOI(MI, MRI, B, false);

  case TargetOpcode::G_FMINNUM:

  case TargetOpcode::G_FMAXNUM:

  case TargetOpcode::G_FMINNUM_IEEE:
@@ -1522,6 +1527,42 @@ bool AMDGPULegalizerInfo::legalizeITOFP( 
  return true;

}



// TODO: Copied from DAG implementation. Verify logic and document how this

// actually works.

bool AMDGPULegalizerInfo::legalizeFPTOI(

  MachineInstr &MI, MachineRegisterInfo &MRI,

  MachineIRBuilder &B, bool Signed) const {

  B.setInstr(MI);



  Register Dst = MI.getOperand(0).getReg();

  Register Src = MI.getOperand(1).getReg();



  const LLT S64 = LLT::scalar(64);

  const LLT S32 = LLT::scalar(32);



  assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S64);



  unsigned Flags = MI.getFlags();



  auto Trunc = B.buildIntrinsicTrunc(S64, Src, Flags);

  auto K0 = B.buildFConstant(S64, BitsToDouble(UINT64_C(0x3df0000000000000)));

  auto K1 = B.buildFConstant(S64, BitsToDouble(UINT64_C(0xc1f0000000000000)));



  auto Mul = B.buildFMul(S64, Trunc, K0, Flags);

  auto FloorMul = B.buildFFloor(S64, Mul, Flags);

  auto Fma = B.buildFMA(S64, FloorMul, K1, Trunc, Flags);



  auto Hi = Signed ?

    B.buildFPTOSI(S32, FloorMul) :

    B.buildFPTOUI(S32, FloorMul);

  auto Lo = B.buildFPTOUI(S32, Fma);



  B.buildMerge(Dst, { Lo.getReg(0), Hi.getReg(0) });

  MI.eraseFromParent();



  return true;

}



bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(

  MachineInstr &MI, MachineRegisterInfo &MRI,

  MachineIRBuilder &B) const {

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

+2 −0
Original line number Diff line number Diff line
@@ -50,6 +50,8 @@ public: 
                              MachineIRBuilder &B) const;

  bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,

                     MachineIRBuilder &B, bool Signed) const;

  bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,

                     MachineIRBuilder &B, bool Signed) const;

  bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,

                            MachineIRBuilder &B) const;

  bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir

+195 −0
Original line number Diff line number Diff line
@@ -159,3 +159,198 @@ body: | 
    %2:_(s32) = G_ANYEXT %1

    $vgpr0 = COPY %2

...



---

name: test_fptosi_s64_s64

body: |

  bb.0:

    liveins: $vgpr0_vgpr1



    ; SI-LABEL: name: test_fptosi_s64_s64

    ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1

    ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)

    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20

    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11

    ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)

    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023

    ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]

    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648

    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]

    ; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495

    ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)

    ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)

    ; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1

    ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]

    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[XOR]]

    ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51

    ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]

    ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]

    ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]

    ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]

    ; SI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]

    ; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000

    ; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000

    ; SI: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C8]]

    ; SI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]

    ; SI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C9]], [[INTRINSIC_TRUNC]]

    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)

    ; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)

    ; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)

    ; SI: $vgpr0_vgpr1 = COPY [[MV1]](s64)

    ; VI-LABEL: name: test_fptosi_s64_s64

    ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1

    ; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]

    ; VI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000

    ; VI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000

    ; VI: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]

    ; VI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]

    ; VI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]

    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)

    ; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)

    ; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)

    ; VI: $vgpr0_vgpr1 = COPY [[MV]](s64)

    %0:_(s64) = COPY $vgpr0_vgpr1

    %1:_(s64) = G_FPTOSI %0

    $vgpr0_vgpr1 = COPY %1

...



---

name: test_fptosi_s64_s64_flags

body: |

  bb.0:

    liveins: $vgpr0_vgpr1



    ; SI-LABEL: name: test_fptosi_s64_s64_flags

    ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1

    ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)

    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20

    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11

    ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)

    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023

    ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]

    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648

    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]

    ; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495

    ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)

    ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)

    ; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1

    ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]

    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[XOR]]

    ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51

    ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]

    ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]

    ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]

    ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]

    ; SI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = nnan G_INTRINSIC_TRUNC [[COPY]]

    ; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000

    ; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000

    ; SI: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[INTRINSIC_TRUNC]], [[C8]]

    ; SI: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]

    ; SI: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FFLOOR]], [[C9]], [[INTRINSIC_TRUNC]]

    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)

    ; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)

    ; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)

    ; SI: $vgpr0_vgpr1 = COPY [[MV1]](s64)

    ; VI-LABEL: name: test_fptosi_s64_s64_flags

    ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1

    ; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = nnan G_INTRINSIC_TRUNC [[COPY]]

    ; VI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000

    ; VI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000

    ; VI: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[INTRINSIC_TRUNC]], [[C]]

    ; VI: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]

    ; VI: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]

    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)

    ; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)

    ; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)

    ; VI: $vgpr0_vgpr1 = COPY [[MV]](s64)

    %0:_(s64) = COPY $vgpr0_vgpr1

    %1:_(s64) = nnan G_FPTOSI %0

    $vgpr0_vgpr1 = COPY %1

...



---

name: test_fptosi_v2s64_to_v2s64

body: |

  bb.0:

    liveins: $vgpr0_vgpr1_vgpr2_vgpr3



    ; SI-LABEL: name: test_fptosi_v2s64_to_v2s64

    ; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3

    ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)

    ; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)

    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20

    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11

    ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)

    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023

    ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]

    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648

    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]

    ; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495

    ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0

    ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)

    ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)

    ; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1

    ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]

    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV]], [[XOR]]

    ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51

    ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]

    ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]

    ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]

    ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]

    ; SI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]

    ; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000

    ; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000

    ; SI: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C8]]

    ; SI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]

    ; SI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C9]], [[INTRINSIC_TRUNC]]

    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)

    ; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)

    ; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)

    ; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)

    ; SI: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)

    ; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[INT1]], [[C2]]

    ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]

    ; SI: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND2]](s32)

    ; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB1]](s32)

    ; SI: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[ASHR1]], [[C6]]

    ; SI: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[XOR1]]

    ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](s32), [[C5]]

    ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](s32), [[C7]]

    ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[MV2]], [[AND3]]

    ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV1]], [[SELECT1]]

    ; SI: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]

    ; SI: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC1]], [[C8]]

    ; SI: [[FFLOOR1:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL1]]

    ; SI: [[FMA1:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR1]], [[C9]], [[INTRINSIC_TRUNC1]]

    ; SI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR1]](s64)

    ; SI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA1]](s64)

    ; SI: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](s32), [[FPTOSI1]](s32)

    ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV1]](s64), [[MV3]](s64)

    ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)

    ; VI-LABEL: name: test_fptosi_v2s64_to_v2s64

    ; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3

    ; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)

    ; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]

    ; VI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000

    ; VI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000

    ; VI: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]

    ; VI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]

    ; VI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]

    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)

    ; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)

    ; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)

    ; VI: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]

    ; VI: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC1]], [[C]]

    ; VI: [[FFLOOR1:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL1]]

    ; VI: [[FMA1:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR1]], [[C1]], [[INTRINSIC_TRUNC1]]

    ; VI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR1]](s64)

    ; VI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA1]](s64)

    ; VI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](s32), [[FPTOSI1]](s32)

    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)

    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)

    %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3

    %1:_(<2 x s64>) = G_FPTOSI %0

    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1

...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir

+195 −0

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