Commit bff8639e authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r238146: 

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r238146 | thomas.stellard | 2015-05-25 12:15:50 -0400 (Mon, 25 May 2015) | 6 lines

R600/SI: Use NAME rather than opName as the key to the MCOpcode tables

This lets us drop a parameter the opName parameter to the VINTRP
multiclass and makes it possible to create multiple VINTRP defs
with the same asm mnemonic.

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llvm-svn: 240284
parent 5add8bbf

llvm/lib/Target/R600/SIInstrInfo.td

+4 −4
Original line number Diff line number Diff line
@@ -1421,16 +1421,16 @@ class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins, 
  VINTRPe_vi <op>,

  SIMCInstr<opName, SISubtarget.VI>;



multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,

multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,

                     string disableEncoding = "", string constraints = "",

                     list<dag> pattern = []> {

  let DisableEncoding = disableEncoding,

      Constraints = constraints in {

    def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;

    def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;



    def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;

    def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;



    def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;

    def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;

  }

}

llvm/lib/Target/R600/SIInstructions.td

+3 −3
Original line number Diff line number Diff line
@@ -1377,14 +1377,14 @@ defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64", 


// FIXME: Specify SchedRW for VINTRP insturctions.

defm V_INTERP_P1_F32 : VINTRP_m <

  0x00000000, "v_interp_p1_f32",

  0x00000000, 

  (outs VGPR_32:$dst),

  (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),

  "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [$m0]",

  "$m0">;



defm V_INTERP_P2_F32 : VINTRP_m <

  0x00000001, "v_interp_p2_f32",

  0x00000001,

  (outs VGPR_32:$dst),

  (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),

  "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
@@ -1392,7 +1392,7 @@ defm V_INTERP_P2_F32 : VINTRP_m < 
  "$src0 = $dst">;



defm V_INTERP_MOV_F32 : VINTRP_m <

  0x00000002, "v_interp_mov_f32",

  0x00000002,

  (outs VGPR_32:$dst),

  (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),

  "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [$m0]",