Commit 5add8bbf authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r237164: 

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r237164 | thomas.stellard | 2015-05-12 14:59:17 -0400 (Tue, 12 May 2015) | 10 lines

R600/SI: Fix bug in VGPR spilling

AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which
caused the srsrc and soffset register to not be set correctly.

This commit replaces the switch statement with a SITargetInfo query
to make sure all spill instructions are covered.

Differential Revision: http://reviews.llvm.org/D9582

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llvm-svn: 240283
parent c08d88a4

llvm/lib/Target/R600/SIDefines.h

+2 −1
Original line number Diff line number Diff line
@@ -36,7 +36,8 @@ enum { 
  DS = 1 << 17,

  MIMG = 1 << 18,

  FLAT = 1 << 19,

  WQM = 1 << 20

  WQM = 1 << 20,

  VGPRSpill = 1 << 21

};

}

llvm/lib/Target/R600/SIInstrFormats.td

+2 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> : 
  field bits<1> MIMG = 0;

  field bits<1> FLAT = 0;

  field bits<1> WQM = 0;

  field bits<1> VGPRSpill = 0;



  // These need to be kept in sync with the enum in SIInstrFlags.

  let TSFlags{0} = VM_CNT;
@@ -66,6 +67,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> : 
  let TSFlags{18} = MIMG;

  let TSFlags{19} = FLAT;

  let TSFlags{20} = WQM;

  let TSFlags{21} = VGPRSpill;



  // Most instructions require adjustments after selection to satisfy

  // operand requirements.

llvm/lib/Target/R600/SIInstrInfo.h

+4 −0
Original line number Diff line number Diff line
@@ -208,6 +208,10 @@ public: 
    return get(Opcode).TSFlags & SIInstrFlags::WQM;

  }



  bool isVGPRSpill(uint16_t Opcode) const {

    return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;

  }



  bool isInlineConstant(const APInt &Imm) const;

  bool isInlineConstant(const MachineOperand &MO) const;

  bool isLiteralConstant(const MachineOperand &MO) const;

llvm/lib/Target/R600/SIInstructions.td

+2 −2
Original line number Diff line number Diff line
@@ -1986,7 +1986,7 @@ defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>; 
defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;



multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {

  let UseNamedOperandTable = 1 in {

  let UseNamedOperandTable = 1, VGPRSpill = 1 in {

    def _SAVE : InstSI <

      (outs),

      (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc,
@@ -1999,7 +1999,7 @@ multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> { 
      (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset),

      "", []

    >;

  } // End UseNamedOperandTable = 1

  } // End UseNamedOperandTable = 1, VGPRSpill = 1

}



defm SI_SPILL_V32  : SI_SPILL_VGPR <VGPR_32>;

llvm/lib/Target/R600/SIPrepareScratchRegs.cpp

+59 −73
Original line number Diff line number Diff line
@@ -128,19 +128,8 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) { 
      MachineInstr &MI = *I;

      RS.forward(I);

      DebugLoc DL = MI.getDebugLoc();

      switch(MI.getOpcode()) {

        default: break;

        case AMDGPU::SI_SPILL_V512_SAVE:

        case AMDGPU::SI_SPILL_V256_SAVE:

        case AMDGPU::SI_SPILL_V128_SAVE:

        case AMDGPU::SI_SPILL_V96_SAVE:

        case AMDGPU::SI_SPILL_V64_SAVE:

        case AMDGPU::SI_SPILL_V32_SAVE:

        case AMDGPU::SI_SPILL_V32_RESTORE:

        case AMDGPU::SI_SPILL_V64_RESTORE:

        case AMDGPU::SI_SPILL_V128_RESTORE:

        case AMDGPU::SI_SPILL_V256_RESTORE:

        case AMDGPU::SI_SPILL_V512_RESTORE:

      if (!TII->isVGPRSpill(MI.getOpcode()))

        continue;



      // Scratch resource

      unsigned ScratchRsrcReg =
@@ -199,9 +188,6 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) { 
      MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));

      MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));

      MI.addOperand(MachineOperand::CreateReg(Rsrc3, false, true, true));



          break;

      }

    }

  }

  return true;