Commit a2684f76 authored by Pengcheng Wang's avatar Pengcheng Wang
Browse files

[RISCV][NFC] Use named arguments in newly added changes 

Named arguments have been supported in D152998 and most *.td files
of RISC-V target have been rewritten. This patch just makes them
consistent since some newly added changes weren't in this way.

Reviewed By: 4vtomat, MaskRay, asb

Differential Revision: https://reviews.llvm.org/D157580
parent c2645925

clang/include/clang/Basic/riscv_sifive_vector.td

+28 −28
Original line number Diff line number Diff line
@@ -72,34 +72,34 @@ multiclass RVVVCIXBuiltinSetWVType<list<string> range, string prototype, 
}



let SupportOverloading = false in {

  defm sf_vc_x_se  : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzUe", [0, 3], /*UseGPR*/1>;

  defm sf_vc_i_se  : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzKz", [2, 3], /*UseGPR*/0>;

  defm sf_vc_xv    : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUe",  [0, 2, 3],  /*UseGPR*/1>;

  defm sf_vc_iv    : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvKz",  [0, 2, 3],  /*UseGPR*/0>;

  defm sf_vc_vv    : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUv",  [0, 2, 3],  /*UseGPR*/0>;

  defm sf_vc_fv    : RVVVCIXBuiltinSet<["si",  "l"], "0KzKzUvFe",  [0, 2, 3],  /*UseGPR*/0>;

  defm sf_vc_xvv   : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUe",  [0, 1, 3],  /*UseGPR*/1>;

  defm sf_vc_ivv   : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvKz",  [0, 1, 3],  /*UseGPR*/0>;

  defm sf_vc_vvv   : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUv",  [0, 1, 3],  /*UseGPR*/0>;

  defm sf_vc_fvv   : RVVVCIXBuiltinSet<["si",  "l"], "0KzUvUvFe",  [0, 1, 3],  /*UseGPR*/0>;

  defm sf_vc_v_x   : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzUe",   [-1, 1, 2], /*UseGPR*/1>;

  defm sf_vc_v_i   : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzKz",   [-1, 1, 2], /*UseGPR*/0>;

  defm sf_vc_v_xv  : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUe",   [-1, 0, 2], /*UseGPR*/1>;

  defm sf_vc_v_iv  : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvKz",   [-1, 0, 2], /*UseGPR*/0>;

  defm sf_vc_v_vv  : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUv",   [-1, 0, 2], /*UseGPR*/0>;

  defm sf_vc_v_fv  : RVVVCIXBuiltinSet<["si",  "l"], "UvKzUvFe",   [-1, 0, 2], /*UseGPR*/0>;

  defm sf_vc_v_xvv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvUe", [-1, 0, 3], /*UseGPR*/1>;

  defm sf_vc_v_ivv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvKz", [-1, 0, 3], /*UseGPR*/0>;

  defm sf_vc_v_vvv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvUv", [-1, 0, 3], /*UseGPR*/0>;

  defm sf_vc_v_fvv : RVVVCIXBuiltinSet<["si",  "l"], "UvKzUvUvFe", [-1, 0, 3], /*UseGPR*/0>;

  defm sf_vc_x_se  : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzUe", [0, 3], UseGPR=1>;

  defm sf_vc_i_se  : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzKz", [2, 3], UseGPR=0>;

  defm sf_vc_xv    : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUe",  [0, 2, 3],  UseGPR=1>;

  defm sf_vc_iv    : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvKz",  [0, 2, 3],  UseGPR=0>;

  defm sf_vc_vv    : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUv",  [0, 2, 3],  UseGPR=0>;

  defm sf_vc_fv    : RVVVCIXBuiltinSet<["si",  "l"], "0KzKzUvFe",  [0, 2, 3],  UseGPR=0>;

  defm sf_vc_xvv   : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUe",  [0, 1, 3],  UseGPR=1>;

  defm sf_vc_ivv   : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvKz",  [0, 1, 3],  UseGPR=0>;

  defm sf_vc_vvv   : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUv",  [0, 1, 3],  UseGPR=0>;

  defm sf_vc_fvv   : RVVVCIXBuiltinSet<["si",  "l"], "0KzUvUvFe",  [0, 1, 3],  UseGPR=0>;

  defm sf_vc_v_x   : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzUe",   [-1, 1, 2], UseGPR=1>;

  defm sf_vc_v_i   : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzKz",   [-1, 1, 2], UseGPR=0>;

  defm sf_vc_v_xv  : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUe",   [-1, 0, 2], UseGPR=1>;

  defm sf_vc_v_iv  : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvKz",   [-1, 0, 2], UseGPR=0>;

  defm sf_vc_v_vv  : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUv",   [-1, 0, 2], UseGPR=0>;

  defm sf_vc_v_fv  : RVVVCIXBuiltinSet<["si",  "l"], "UvKzUvFe",   [-1, 0, 2], UseGPR=0>;

  defm sf_vc_v_xvv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvUe", [-1, 0, 3], UseGPR=1>;

  defm sf_vc_v_ivv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvKz", [-1, 0, 3], UseGPR=0>;

  defm sf_vc_v_vvv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvUv", [-1, 0, 3], UseGPR=0>;

  defm sf_vc_v_fvv : RVVVCIXBuiltinSet<["si",  "l"], "UvKzUvUvFe", [-1, 0, 3], UseGPR=0>;

  let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {

    defm sf_vc_xvw   : RVVVCIXBuiltinSet<["csi"], "0KzUwUvUe",  [0, 1, 2, 3],  /*UseGPR*/1>;

    defm sf_vc_ivw   : RVVVCIXBuiltinSet<["csi"], "0KzUwUvKz",  [0, 1, 2, 3],  /*UseGPR*/0>;

    defm sf_vc_vvw   : RVVVCIXBuiltinSet<["csi"], "0KzUwUvUv",  [0, 1, 2, 3],  /*UseGPR*/0>;

    defm sf_vc_fvw   : RVVVCIXBuiltinSet<["si"],  "0KzUwUvFe",  [0, 1, 2, 3],  /*UseGPR*/0>;

    defm sf_vc_v_xvw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvUe", [-1, 0, 2, 3], /*UseGPR*/1>;

    defm sf_vc_v_ivw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvKz", [-1, 0, 2, 3], /*UseGPR*/0>;

    defm sf_vc_v_vvw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvUv", [-1, 0, 2, 3], /*UseGPR*/0>;

    defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"],  "UwKzUwUvFe", [-1, 0, 2, 3], /*UseGPR*/0>;

    defm sf_vc_xvw   : RVVVCIXBuiltinSet<["csi"], "0KzUwUvUe",  [0, 1, 2, 3],  UseGPR=1>;

    defm sf_vc_ivw   : RVVVCIXBuiltinSet<["csi"], "0KzUwUvKz",  [0, 1, 2, 3],  UseGPR=0>;

    defm sf_vc_vvw   : RVVVCIXBuiltinSet<["csi"], "0KzUwUvUv",  [0, 1, 2, 3],  UseGPR=0>;

    defm sf_vc_fvw   : RVVVCIXBuiltinSet<["si"],  "0KzUwUvFe",  [0, 1, 2, 3],  UseGPR=0>;

    defm sf_vc_v_xvw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvUe", [-1, 0, 2, 3], UseGPR=1>;

    defm sf_vc_v_ivw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvKz", [-1, 0, 2, 3], UseGPR=0>;

    defm sf_vc_v_vvw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvUv", [-1, 0, 2, 3], UseGPR=0>;

    defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"],  "UwKzUwUvFe", [-1, 0, 2, 3], UseGPR=0>;

  }

}

clang/include/clang/Basic/riscv_vector.td

+2 −2
Original line number Diff line number Diff line
@@ -2895,7 +2895,7 @@ let UnMaskedPolicyScheme = HasPassthruOperand in { 
let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {

  // zvkg

  defm vghsh   : RVVOutOp2BuiltinSetVVZvk;

  defm vgmul   : RVVOutBuiltinSetZvk</*HasVV*/1, /*HasVS*/0>;

  defm vgmul   : RVVOutBuiltinSetZvk<HasVV=1, HasVS=0>;



  // zvkned

  defm vaesdf  : RVVOutBuiltinSetZvk;
@@ -2905,7 +2905,7 @@ let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in { 
  let UnMaskedPolicyScheme = HasPassthruOperand in

  defm vaeskf1 : RVVOutOp1BuiltinSet<"vaeskf1", "i", [["vi", "Uv", "UvUvKz"]]>;

  defm vaeskf2 : RVVOutOp2BuiltinSetVIZvk;

  defm vaesz   : RVVOutBuiltinSetZvk</*HasVV*/0>;

  defm vaesz   : RVVOutBuiltinSetZvk<HasVV=0>;



  // zvknha or zvknhb

  defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"il">;

llvm/include/llvm/IR/IntrinsicsRISCV.td

+8 −8
Original line number Diff line number Diff line
@@ -308,10 +308,10 @@ let TargetPrefix = "riscv" in { 


  multiclass RISCVUnaryAAUnMaskedZvk<bit HasVV = 1, bit HasVS = 1> {

    if HasVV then

      def "int_riscv_" # NAME # "_vv" : RISCVUnaryAAUnMaskedZvk</*IsVS*/0>;

      def "int_riscv_" # NAME # "_vv" : RISCVUnaryAAUnMaskedZvk<IsVS=0>;



    if HasVS then

      def "int_riscv_" # NAME # "_vs" : RISCVUnaryAAUnMaskedZvk</*IsVS*/1>;

      def "int_riscv_" # NAME # "_vs" : RISCVUnaryAAUnMaskedZvk<IsVS=1>;

  }

  // For destination vector type is the same as first source vector (with mask).

  // Input: (vector_in, vector_in, mask, vl, policy)
@@ -1848,16 +1848,16 @@ let TargetPrefix = "riscv" in { 


  // Zvkg

  def int_riscv_vghsh    : RISCVBinaryAAXUnMaskedZvk;

  def int_riscv_vgmul_vv : RISCVUnaryAAUnMaskedZvk</*IsVS*/0>;

  def int_riscv_vgmul_vv : RISCVUnaryAAUnMaskedZvk<IsVS=0>;



  // Zvkned

  defm vaesdf            : RISCVUnaryAAUnMaskedZvk;

  defm vaesdm            : RISCVUnaryAAUnMaskedZvk;

  defm vaesef            : RISCVUnaryAAUnMaskedZvk;

  defm vaesem            : RISCVUnaryAAUnMaskedZvk;

  def int_riscv_vaeskf1  : RISCVBinaryAAXUnMasked</*IsVI*/1>;

  def int_riscv_vaeskf2  : RISCVBinaryAAXUnMaskedZvk</*IsVI*/1>;

  defm vaesz             : RISCVUnaryAAUnMaskedZvk</*HasVV*/0>;

  def int_riscv_vaeskf1  : RISCVBinaryAAXUnMasked<IsVI=1>;

  def int_riscv_vaeskf2  : RISCVBinaryAAXUnMaskedZvk<IsVI=1>;

  defm vaesz             : RISCVUnaryAAUnMaskedZvk<HasVV=0>;



  // Zvknha or Zvknhb

  def int_riscv_vsha2ch  : RISCVBinaryAAXUnMaskedZvk;
@@ -1865,11 +1865,11 @@ let TargetPrefix = "riscv" in { 
  def int_riscv_vsha2ms  : RISCVBinaryAAXUnMaskedZvk;



  // Zvksed

  def int_riscv_vsm4k    : RISCVBinaryAAXUnMasked</*IsVI*/1>;

  def int_riscv_vsm4k    : RISCVBinaryAAXUnMasked<IsVI=1>;

  defm vsm4r             : RISCVUnaryAAUnMaskedZvk;



  // Zvksh

  def int_riscv_vsm3c    : RISCVBinaryAAXUnMaskedZvk</*IsVI*/1>;

  def int_riscv_vsm3c    : RISCVBinaryAAXUnMaskedZvk<IsVI=1>;

  def int_riscv_vsm3me   : RISCVBinaryAAXUnMasked;

} // TargetPrefix = "riscv"

llvm/include/llvm/IR/IntrinsicsRISCVXsf.td

+12 −12
Original line number Diff line number Diff line
@@ -93,38 +93,38 @@ let TargetPrefix = "riscv" in { 
      defvar range = ["c", "s", "i", "l"];

      foreach r = range in {

        foreach s = VCIXSuffix<r>.suffix in {

          def "int_riscv_sf_vc_" # t # "_se_" # s : RISCVSFCustomVC_X</*HasDst*/0, /*HasSE*/1, ImmScalar>;

          def "int_riscv_sf_vc_" # t # "_se_" # s : RISCVSFCustomVC_X<HasDst=0, HasSE=1, ImmScalar=ImmScalar>;

        }

      }

      def "int_riscv_sf_vc_v_" # t # "_se" : RISCVSFCustomVC_X</*HasDst*/1, /*HasSE*/1, ImmScalar>;

      def "int_riscv_sf_vc_v_" # t         : RISCVSFCustomVC_X</*HasDst*/1, /*HasSE*/0, ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "_se" : RISCVSFCustomVC_X<HasDst=1, HasSE=1, ImmScalar=ImmScalar>;

      def "int_riscv_sf_vc_v_" # t         : RISCVSFCustomVC_X<HasDst=1, HasSE=0, ImmScalar=ImmScalar>;

    }

  }



  multiclass RISCVSFCustomVC_XV<list<string> type> {

    foreach t = type in {

      defvar ImmScalar = !eq(t, "i");

      def "int_riscv_sf_vc_" # t # "v_se"   : RISCVSFCustomVC_XV</*HasDst*/0, /*HasSE*/1, ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "v_se" : RISCVSFCustomVC_XV</*HasDst*/1, /*HasSE*/1, ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "v"    : RISCVSFCustomVC_XV</*HasDst*/1, /*HasSE*/0, ImmScalar>;

      def "int_riscv_sf_vc_" # t # "v_se"   : RISCVSFCustomVC_XV<HasDst=0, HasSE=1, ImmScalar=ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "v_se" : RISCVSFCustomVC_XV<HasDst=1, HasSE=1, ImmScalar=ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "v"    : RISCVSFCustomVC_XV<HasDst=1, HasSE=0, ImmScalar=ImmScalar>;

    }

  }



  multiclass RISCVSFCustomVC_XVV<list<string> type> {

    foreach t = type in {

      defvar ImmScalar = !eq(t, "i");

      def "int_riscv_sf_vc_" # t # "vv_se"   : RISCVSFCustomVC_XVV</*HasDst*/0, /*HasSE*/1, ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "vv_se" : RISCVSFCustomVC_XVV</*HasDst*/1, /*HasSE*/1, ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "vv"    : RISCVSFCustomVC_XVV</*HasDst*/1, /*HasSE*/0, ImmScalar>;

      def "int_riscv_sf_vc_" # t # "vv_se"   : RISCVSFCustomVC_XVV<HasDst=0, HasSE=1, ImmScalar=ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "vv_se" : RISCVSFCustomVC_XVV<HasDst=1, HasSE=1, ImmScalar=ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "vv"    : RISCVSFCustomVC_XVV<HasDst=1, HasSE=0, ImmScalar=ImmScalar>;

    }

  }



  multiclass RISCVSFCustomVC_XVW<list<string> type> {

    foreach t = type in {

      defvar ImmScalar = !eq(t, "i");

      def "int_riscv_sf_vc_" # t # "vw_se"   : RISCVSFCustomVC_XVW</*HasDst*/0, /*HasSE*/1, ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "vw_se" : RISCVSFCustomVC_XVW</*HasDst*/1, /*HasSE*/1, ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "vw"    : RISCVSFCustomVC_XVW</*HasDst*/1, /*HasSE*/0, ImmScalar>;

      def "int_riscv_sf_vc_" # t # "vw_se"   : RISCVSFCustomVC_XVW<HasDst=0, HasSE=1, ImmScalar=ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "vw_se" : RISCVSFCustomVC_XVW<HasDst=1, HasSE=1, ImmScalar=ImmScalar>;

      def "int_riscv_sf_vc_v_" # t # "vw"    : RISCVSFCustomVC_XVW<HasDst=1, HasSE=0, ImmScalar=ImmScalar>;

    }

  }

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

+3 −3
Original line number Diff line number Diff line
@@ -620,7 +620,7 @@ multiclass VWMAC_MV_X<string opcodestr, bits<6> funct6> { 
multiclass VWMAC_MV_V_X<string opcodestr, bits<6> funct6>

   : VWMAC_MV_X<opcodestr, funct6> {

  let RVVConstraint = WidenV in

  def V : VALUrVV<funct6, OPMVV, opcodestr # ".vv", /*EarlyClobber*/1>,

  def V : VALUrVV<funct6, OPMVV, opcodestr # ".vv", EarlyClobber=1>,

          SchedTernaryMC<"WriteVIWMulAddV", "ReadVIWMulAddV", "ReadVIWMulAddV",

                         "ReadVIWMulAddV">;

}
@@ -721,10 +721,10 @@ multiclass VMAC_FV_V_F<string opcodestr, bits<6> funct6> { 


multiclass VWMAC_FV_V_F<string opcodestr, bits<6> funct6> {

  let RVVConstraint = WidenV in {

  def V : VALUrVV<funct6, OPFVV, opcodestr # ".vv", /*EarlyClobber*/1>,

  def V : VALUrVV<funct6, OPFVV, opcodestr # ".vv", EarlyClobber=1>,

          SchedTernaryMC<"WriteVFWMulAddV", "ReadVFWMulAddV", "ReadVFWMulAddV",

                         "ReadVFWMulAddV">;

  def F : VALUrVF<funct6, OPFVF, opcodestr # ".vf", /*EarlyClobber*/1>,

  def F : VALUrVF<funct6, OPFVF, opcodestr # ".vf", EarlyClobber=1>,

          SchedTernaryMC<"WriteVFWMulAddF", "ReadVFWMulAddV", "ReadVFWMulAddF",

                         "ReadVFWMulAddV">;

  }