Commit 9a24488c authored by Fangrui Song's avatar Fangrui Song
Browse files

[CodeGen] Move fentry-insert, xray-instrumentation and patchable-function before addPreEmitPass() 

This intention is to move patchable-function before aarch64-branch-targets
(configured in AArch64PassConfig::addPreEmitPass) so that we emit BTI before NOPs
(see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92424).

This also allows addPreEmitPass() passes to know the precise instruction sizes if they want.

Tried x86-64 Debug/Release builds of ccls with -fxray-instrument -fxray-instruction-threshold=1.
No output difference with this commit and the previous commit.
parent a72d15e3

llvm/lib/CodeGen/TargetPassConfig.cpp

+6 −6
Original line number Diff line number Diff line
@@ -956,6 +956,12 @@ void TargetPassConfig::addMachinePasses() { 
  if (getOptLevel() != CodeGenOpt::None)

    addBlockPlacement();



  // Insert before XRay Instrumentation.

  addPass(&FEntryInserterID, false);



  addPass(&XRayInstrumentationID, false);

  addPass(&PatchableFunctionID, false);



  addPreEmitPass();



  if (TM->Options.EnableIPRA)
@@ -968,12 +974,6 @@ void TargetPassConfig::addMachinePasses() { 
  addPass(&StackMapLivenessID, false);

  addPass(&LiveDebugValuesID, false);



  // Insert before XRay Instrumentation.

  addPass(&FEntryInserterID, false);



  addPass(&XRayInstrumentationID, false);

  addPass(&PatchableFunctionID, false);



  if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&

      EnableMachineOutliner != NeverOutline) {

    bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);

llvm/test/CodeGen/AArch64/O0-pipeline.ll

+3 −3
Original line number Diff line number Diff line
@@ -63,14 +63,14 @@ 
; CHECK-NEXT:       AArch64 pseudo instruction expansion pass

; CHECK-NEXT:       AArch64 speculation hardening pass

; CHECK-NEXT:       Analyze Machine Code For Garbage Collection

; CHECK-NEXT:       Insert fentry calls

; CHECK-NEXT:       Insert XRay ops

; CHECK-NEXT:       Implement the 'patchable-function' attribute

; CHECK-NEXT:       AArch64 Branch Targets

; CHECK-NEXT:       Branch relaxation pass

; CHECK-NEXT:       Contiguously Lay Out Funclets

; CHECK-NEXT:       StackMap Liveness Analysis

; CHECK-NEXT:       Live DEBUG_VALUE analysis

; CHECK-NEXT:       Insert fentry calls

; CHECK-NEXT:       Insert XRay ops

; CHECK-NEXT:       Implement the 'patchable-function' attribute

; CHECK-NEXT:       Lazy Machine Block Frequency Analysis

; CHECK-NEXT:       Machine Optimization Remark Emitter

; CHECK-NEXT:       AArch64 Assembly Printer

llvm/test/CodeGen/AArch64/O3-pipeline.ll

+3 −3
Original line number Diff line number Diff line
@@ -171,6 +171,9 @@ 
; CHECK-NEXT:       Machine Block Frequency Analysis

; CHECK-NEXT:       MachinePostDominator Tree Construction

; CHECK-NEXT:       Branch Probability Basic Block Placement

; CHECK-NEXT:       Insert fentry calls

; CHECK-NEXT:       Insert XRay ops

; CHECK-NEXT:       Implement the 'patchable-function' attribute

; CHECK-NEXT:       AArch64 load / store optimization pass

; CHECK-NEXT:       AArch64 Branch Targets

; CHECK-NEXT:       Branch relaxation pass
@@ -178,9 +181,6 @@ 
; CHECK-NEXT:       Contiguously Lay Out Funclets

; CHECK-NEXT:       StackMap Liveness Analysis

; CHECK-NEXT:       Live DEBUG_VALUE analysis

; CHECK-NEXT:       Insert fentry calls

; CHECK-NEXT:       Insert XRay ops

; CHECK-NEXT:       Implement the 'patchable-function' attribute

; CHECK-NEXT:     Machine Outliner

; CHECK-NEXT:     FunctionPass Manager

; CHECK-NEXT:       Lazy Machine Block Frequency Analysis

llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll

0 → 100644
+24 −0
Original line number Diff line number Diff line 
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck --check-prefixes=CHECK %s



define i32 @f0() "patchable-function-entry"="0" "branch-target-enforcement" {

; CHECK-LABEL: f0:

; CHECK-NEXT: .Lfunc_begin0:

; CHECK:       hint #34

; CHECK-NEXT:  mov w0, wzr

; CHECK:       .section __patchable_function_entries,"awo",@progbits,f0,unique,0

; CHECK-NEXT:  .p2align 3

; CHECK-NEXT:  .xword .Lfunc_begin0

  ret i32 0

}



define i32 @f1() "patchable-function-entry"="1" "branch-target-enforcement" {

; CHECK-LABEL: f1:

; CHECK-NEXT: .Lfunc_begin1:

; CHECK:       hint #34

; CHECK-NEXT:  nop

; CHECK-NEXT:  mov w0, wzr

; CHECK:       .section __patchable_function_entries,"awo",@progbits,f0,unique,0

; CHECK-NEXT:  .p2align 3

; CHECK-NEXT:  .xword .Lfunc_begin1

  ret i32 0

}

llvm/test/CodeGen/ARM/O3-pipeline.ll

+3 −3
Original line number Diff line number Diff line
@@ -156,6 +156,9 @@ 
; CHECK-NEXT:      Machine Block Frequency Analysis

; CHECK-NEXT:      MachinePostDominator Tree Construction

; CHECK-NEXT:      Branch Probability Basic Block Placement

; CHECK-NEXT:      Insert fentry calls

; CHECK-NEXT:      Insert XRay ops

; CHECK-NEXT:      Implement the 'patchable-function' attribute

; CHECK-NEXT:      Thumb2 instruction size reduce pass

; CHECK-NEXT:      Unpack machine instruction bundles

; CHECK-NEXT:      optimise barriers pass
@@ -168,9 +171,6 @@ 
; CHECK-NEXT:      Contiguously Lay Out Funclets

; CHECK-NEXT:      StackMap Liveness Analysis

; CHECK-NEXT:      Live DEBUG_VALUE analysis

; CHECK-NEXT:      Insert fentry calls

; CHECK-NEXT:      Insert XRay ops

; CHECK-NEXT:      Implement the 'patchable-function' attribute

; CHECK-NEXT:      Lazy Machine Block Frequency Analysis

; CHECK-NEXT:      Machine Optimization Remark Emitter

; CHECK-NEXT:      ARM Assembly Printer