Commit 94e8ef4d authored by Matt Arsenault's avatar Matt Arsenault
Browse files

AMDGPU/GlobalISel: Look through copies for source modifiers 

When all VOP instructions are legalized to VGPRs, any SGPR source
modifiers will have a copy in the way.
parent c2ad7ee1

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

+2 −2
Original line number Diff line number Diff line
@@ -1990,12 +1990,12 @@ std::pair<Register, unsigned> 
AMDGPUInstructionSelector::selectVOP3ModsImpl(

  Register Src) const {

  unsigned Mods = 0;

  MachineInstr *MI = MRI->getVRegDef(Src);

  MachineInstr *MI = getDefIgnoringCopies(Src, *MRI);



  if (MI && MI->getOpcode() == AMDGPU::G_FNEG) {

    Src = MI->getOperand(1).getReg();

    Mods |= SISrcMods::NEG;

    MI = MRI->getVRegDef(Src);

    MI = getDefIgnoringCopies(Src, *MRI);

  }



  if (MI && MI->getOpcode() == AMDGPU::G_FABS) {

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir

+2 −9
Original line number Diff line number Diff line
@@ -165,10 +165,7 @@ body: | 
    ; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_XOR_B32_]]

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $exec

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
@@ -193,11 +190,7 @@ body: | 
    ; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647

    ; GFX6: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc

    ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[S_AND_B32_]], [[S_MOV_B32_1]], implicit-def $scc

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[S_XOR_B32_]], 0, 0, implicit $exec

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir

+1 −7
Original line number Diff line number Diff line
@@ -166,13 +166,7 @@ body: | 
    ; GFX6-LABEL: name: fadd_s64_fneg_copy_sgpr

    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0

    ; GFX6: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1

    ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY3]], [[S_MOV_B32_]], implicit-def $scc

    ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1

    ; GFX6: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY4]], 0, 0, implicit $exec

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:sgpr(s64) = COPY $sgpr0_sgpr1

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir

+3 −9
Original line number Diff line number Diff line
@@ -206,26 +206,20 @@ body: | 
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX6: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec

    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec

    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX9-DL-LABEL: name: fma_f32_copy_fneg_src2

    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX9-DL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX9-DL: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec

    ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec

    ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec

    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX10-LABEL: name: fma_f32_copy_fneg_src2

    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX10: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec

    ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec

    ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir

+2 −6
Original line number Diff line number Diff line
@@ -175,18 +175,14 @@ body: | 
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX6: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec

    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec

    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    ; GFX10-LABEL: name: fmad_f32_copy_fneg_src2

    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX10: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY2]], implicit $exec

    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 0, [[V_XOR_B32_e32_]], 0, 0, implicit $exec

    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1