Commit 91618d94 authored by Huihui Zhang's avatar Huihui Zhang
Browse files

[ARM] Fix data race on RegisterBank initialization. 

Summary:
The initialization of RegisterBank needs to be done only once. The
logic of AlreadyInit has data race, use llvm::call_once instead.

This is continuing work of D73587.

Reviewers: arsenm, rovka, dsanders, t.p.northover, efriedma, apazos

Reviewed By: arsenm

Subscribers: wdng, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73605
parent 8bb6c8a2

llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp

+31 −29
Original line number Diff line number Diff line
@@ -131,16 +131,14 @@ static void checkValueMappings() { 


ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)

    : ARMGenRegisterBankInfo() {

  static bool AlreadyInit = false;

  // We have only one set of register banks, whatever the subtarget

  // is. Therefore, the initialization of the RegBanks table should be

  // done only once. Indeed the table of all register banks

  // (ARM::RegBanks) is unique in the compiler. At some point, it

  // will get tablegen'ed and the whole constructor becomes empty.

  if (AlreadyInit)

    return;

  AlreadyInit = true;

  static llvm::once_flag InitializeRegisterBankFlag;



  static auto InitializeRegisterBankOnce = [this](const auto &TRI) {

    const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);

    (void)RBGPR;

    assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
@@ -160,7 +158,8 @@ ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI) 
           "Subclass not added?");

    assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&

           "Subclass not added?");

  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) &&

    assert(RBGPR.covers(

               *TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) &&

           "Subclass not added?");

    assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&

           "Subclass not added?");
@@ -170,6 +169,9 @@ ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI) 
    ARM::checkPartialMappings();

    ARM::checkValueMappings();

#endif

  };



  llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce, TRI);

}



const RegisterBank &