Commit 658081ea authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r248858: 



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r248858 | marek.olsak | 2015-09-29 19:37:32 -0400 (Tue, 29 Sep 2015) | 9 lines

AMDGPU/SI: Don't set DATA_FORMAT if ADD_TID_ENABLE is set

to prevent setting a huge stride, because DATA_FORMAT has a different
meaning if ADD_TID_ENABLE is set.

This is a candidate for stable llvm 3.7.

Tested-and-Reviewed-by: default avatarChristian König <christian.koenig@amd.com>

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llvm-svn: 253236
parent 7af89296

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

+1 −3
Original line number Diff line number Diff line
@@ -2253,10 +2253,8 @@ MachineSDNode *SITargetLowering::buildScratchRSRC(SelectionDAG &DAG, 
                                                  SDValue Ptr) const {

  const SIInstrInfo *TII =

      static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());

  uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE |

                  0xffffffff; // Size



  return buildRSRC(DAG, DL, Ptr, 0, Rsrc);

  return buildRSRC(DAG, DL, Ptr, 0, TII->getScratchRsrcWords23());

}



SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+13 −0
Original line number Diff line number Diff line
@@ -2778,3 +2778,16 @@ uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const { 


  return RsrcDataFormat;

}



uint64_t SIInstrInfo::getScratchRsrcWords23() const {

  uint64_t Rsrc23 = getDefaultRsrcDataFormat() |

                    AMDGPU::RSRC_TID_ENABLE |

                    0xffffffff; // Size;



  // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].

  // Clear them unless we want a huge stride.

  if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)

    Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;



  return Rsrc23;

}

llvm/lib/Target/AMDGPU/SIInstrInfo.h

+1 −1
Original line number Diff line number Diff line
@@ -353,7 +353,7 @@ public: 
  }



  uint64_t getDefaultRsrcDataFormat() const;



  uint64_t getScratchRsrcWords23() const;

};



namespace AMDGPU {

llvm/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp

+3 −4
Original line number Diff line number Diff line
@@ -135,8 +135,7 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) { 
      unsigned ScratchRsrcReg =

          RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);



      uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |

                      0xffffffff; // Size

      uint64_t Rsrc23 = TII->getScratchRsrcWords23();



      unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);

      unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
@@ -152,11 +151,11 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) { 
              .addReg(ScratchRsrcReg, RegState::ImplicitDefine);



      BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)

              .addImm(Rsrc & 0xffffffff)

              .addImm(Rsrc23 & 0xffffffff)

              .addReg(ScratchRsrcReg, RegState::ImplicitDefine);



      BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)

              .addImm(Rsrc >> 32)

              .addImm(Rsrc23 >> 32)

              .addReg(ScratchRsrcReg, RegState::ImplicitDefine);



      // Scratch Offset