Commit 7af89296 authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r246051: 

------------------------------------------------------------------------
r246051 | Matthew.Arsenault | 2015-08-26 14:54:50 -0400 (Wed, 26 Aug 2015) | 6 lines

AMDGPU: Make sure to reserve super registers

I think this could potentially have broken if
one of the super registers were allocated
that contain v254/v255.

------------------------------------------------------------------------

llvm-svn: 253235
parent 1ce7e7c5

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

+15 −16
Original line number Diff line number Diff line
@@ -26,23 +26,25 @@ using namespace llvm; 


SIRegisterInfo::SIRegisterInfo() : AMDGPURegisterInfo() {}



BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {

  BitVector Reserved(getNumRegs());

  Reserved.set(AMDGPU::EXEC);

void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {

  MCRegAliasIterator R(Reg, this, true);



  // EXEC_LO and EXEC_HI could be allocated and used as regular register,

  // but this seems likely to result in bugs, so I'm marking them as reserved.

  Reserved.set(AMDGPU::EXEC_LO);

  Reserved.set(AMDGPU::EXEC_HI);

  for (; R.isValid(); ++R)

    Reserved.set(*R);

}



BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {

  BitVector Reserved(getNumRegs());

  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);

  Reserved.set(AMDGPU::FLAT_SCR);

  Reserved.set(AMDGPU::FLAT_SCR_LO);

  Reserved.set(AMDGPU::FLAT_SCR_HI);



  // EXEC_LO and EXEC_HI could be allocated and used as regular register, but

  // this seems likely to result in bugs, so I'm marking them as reserved.

  reserveRegisterTuples(Reserved, AMDGPU::EXEC);

  reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);



  // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs

  Reserved.set(AMDGPU::VGPR255);

  Reserved.set(AMDGPU::VGPR254);

  reserveRegisterTuples(Reserved, AMDGPU::VGPR254);

  reserveRegisterTuples(Reserved, AMDGPU::VGPR255);



  // Tonga and Iceland can only allocate a fixed number of SGPRs due

  // to a hw bug.
@@ -54,10 +56,7 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 


    for (unsigned i = Limit; i < NumSGPRs; ++i) {

      unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);

      MCRegAliasIterator R = MCRegAliasIterator(Reg, this, true);



      for (; R.isValid(); ++R)

        Reserved.set(*R);

      reserveRegisterTuples(Reserved, Reg);

    }

  }

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

+3 −0
Original line number Diff line number Diff line
@@ -23,7 +23,10 @@ 
namespace llvm {



struct SIRegisterInfo : public AMDGPURegisterInfo {

private:

  void reserveRegisterTuples(BitVector &, unsigned Reg) const;



public:

  SIRegisterInfo();



  BitVector getReservedRegs(const MachineFunction &MF) const override;