Commit 64771cf1 authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r329852: 

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r329852 | nemanjai | 2018-04-11 14:25:44 -0700 (Wed, 11 Apr 2018) | 8 lines

[PowerPC] Fix condition for 64-bit rotate when replacing r+r instr with r+i

This patch fixes https://bugs.llvm.org/show_bug.cgi?id=37039
The condition only covers one of the two 64-bit rotate instructions. This just
adds the second (RLDICLo).

Patch by Josh Stone.

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llvm-svn: 330076
parent 28816ba3

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

+2 −1
Original line number Diff line number Diff line
@@ -2431,7 +2431,8 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI, 
    // Use APInt's rotate function.

    int64_t SH = MI.getOperand(2).getImm();

    int64_t MB = MI.getOperand(3).getImm();

    APInt InVal(Opc == PPC::RLDICL ? 64 : 32, SExtImm, true);

    APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?

                64 : 32, SExtImm, true);

    InVal = InVal.rotl(SH);

    uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;

    InVal &= Mask;

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

+64 −0
Original line number Diff line number Diff line
@@ -560,6 +560,16 @@ 
    ret i64 %cond

  }

  

  ; Function Attrs: norecurse nounwind readnone

  define i64 @testRLDICLo3(i64 %a, i64 %b) local_unnamed_addr #0 {

  entry:

    %shr = lshr i64 %a, 11

    %and = and i64 %shr, 16777215

    %tobool = icmp eq i64 %and, 0

    %cond = select i1 %tobool, i64 %b, i64 %and

    ret i64 %cond

  }

  

  ; Function Attrs: norecurse nounwind readnone

  define zeroext i32 @testRLWINM(i32 zeroext %a) local_unnamed_addr #0 {

  entry:
@@ -3902,6 +3912,60 @@ body: | 
    %x3 = COPY %4

    BLR8 implicit %lr8, implicit %rm, implicit %x3



...

---

name:            testRLDICLo3

# CHECK-ALL: name: testRLDICLo3

alignment:       4

exposesReturnsTwice: false

legalized:       false

regBankSelected: false

selected:        false

tracksRegLiveness: true

registers:       

  - { id: 0, class: g8rc, preferred-register: '' }

  - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }

  - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }

  - { id: 3, class: crrc, preferred-register: '' }

  - { id: 4, class: g8rc, preferred-register: '' }

liveins:         

  - { reg: '%x3', virtual-reg: '%0' }

  - { reg: '%x4', virtual-reg: '%1' }

frameInfo:       

  isFrameAddressTaken: false

  isReturnAddressTaken: false

  hasStackMap:     false

  hasPatchPoint:   false

  stackSize:       0

  offsetAdjustment: 0

  maxAlignment:    0

  adjustsStack:    false

  hasCalls:        false

  stackProtector:  ''

  maxCallFrameSize: 4294967295

  hasOpaqueSPAdjustment: false

  hasVAStart:      false

  hasMustTailInVarArgFunc: false

  savePoint:       ''

  restorePoint:    ''

fixedStack:      

stack:           

constants:       

body:             |

  bb.0.entry:

    liveins: %x3, %x4

  

    %1 = COPY %x4

    %0 = LI8 2

    %2 = RLDICLo %0, 32, 32, implicit-def %cr0

    ; CHECK: ANDIo8 %0, 0

    ; CHECK-LATE: li 3, 2

    ; CHECK-LATE: andi. 3, 3, 0

    %3 = COPY killed %cr0

    %4 = ISEL8 %1, %2, %3.sub_eq

    %x3 = COPY %4

    BLR8 implicit %lr8, implicit %rm, implicit %x3



...

---

name:            testRLWINM