Commit 28816ba3 authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r329359 and r329363: 

------------------------------------------------------------------------
r329359 | manojgupta | 2018-04-05 15:47:25 -0700 (Thu, 05 Apr 2018) | 11 lines

Attempt to fix Mips breakages.

Summary:
Replace ArrayRefs by actual std::array objects so that there are
no dangling references.

Reviewers: rsmith, gkistanova

Subscribers: sdardis, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D45338
------------------------------------------------------------------------

------------------------------------------------------------------------
r329363 | manojgupta | 2018-04-05 16:23:29 -0700 (Thu, 05 Apr 2018) | 5 lines

Fix lld-x86_64-darwin13 build fails.

Use double braces in std::array initialization
to keep Darwin builders happy.

------------------------------------------------------------------------

llvm-svn: 329859
parent 9af1b339

llvm/lib/Target/Mips/MipsFastISel.cpp

+8 −7
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ 
#include "llvm/Support/MathExtras.h"

#include "llvm/Support/raw_ostream.h"

#include <algorithm>

#include <array>

#include <cassert>

#include <cstdint>
@@ -1306,13 +1307,13 @@ bool MipsFastISel::fastLowerArguments() { 
    return false;

  }



  const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,

                                            Mips::A3};

  const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14};

  const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7};

  ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin();

  ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin();

  ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin();

  std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,

                                           Mips::A3}};

  std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};

  std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};

  auto NextGPR32 = GPR32ArgRegs.begin();

  auto NextFGR32 = FGR32ArgRegs.begin();

  auto NextAFGR64 = AFGR64ArgRegs.begin();



  struct AllocatedReg {

    const TargetRegisterClass *RC;