Commit 64734c43 authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r322373: 

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r322373 | d0k | 2018-01-12 07:03:24 -0800 (Fri, 12 Jan 2018) | 4 lines

[PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate

I'm not even sure if this transform is ever worth it, but this at least
stops the bleeding.
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llvm-svn: 330082
parent 64771cf1

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

+4 −0
Original line number Diff line number Diff line
@@ -2445,6 +2445,8 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI, 
      Is64BitLI = Opc != PPC::RLDICL_32;

      NewImm = InVal.getSExtValue();

      SetCR = Opc == PPC::RLDICLo;

      if (SetCR && (SExtImm & NewImm) != NewImm)

        return false;

      break;

    }

    return false;
@@ -2472,6 +2474,8 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI, 
      Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;

      NewImm = InVal.getSExtValue();

      SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;

      if (SetCR && (SExtImm & NewImm) != NewImm)

        return false;

      break;

    }

    return false;

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

+134 −0
Original line number Diff line number Diff line
@@ -561,6 +561,15 @@ 
  }

  

  ; Function Attrs: norecurse nounwind readnone

  define i64 @testRLDICLo2(i64 %a, i64 %b) local_unnamed_addr #0 {

  entry:

    %shr = lshr i64 %a, 11

    %and = and i64 %shr, 16777215

    %tobool = icmp eq i64 %and, 0

    %cond = select i1 %tobool, i64 %b, i64 %and

    ret i64 %cond

  }



  define i64 @testRLDICLo3(i64 %a, i64 %b) local_unnamed_addr #0 {

  entry:

    %shr = lshr i64 %a, 11
@@ -611,6 +620,15 @@ 
    ret i32 %cond

  }

  

  ; Function Attrs: norecurse nounwind readnone

  define zeroext i32 @testRLWINMo2(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {

  entry:

    %and = and i32 %a, 255

    %tobool = icmp eq i32 %and, 0

    %cond = select i1 %tobool, i32 %b, i32 %a

    ret i32 %cond

  }



  ; Function Attrs: norecurse nounwind readnone

  define i64 @testRLWINM8o(i64 %a, i64 %b) local_unnamed_addr #0 {

  entry:
@@ -3912,6 +3930,59 @@ body: | 
    %x3 = COPY %4

    BLR8 implicit %lr8, implicit %rm, implicit %x3



...

---

name:            testRLDICLo2

# CHECK-ALL: name: testRLDICLo2

alignment:       4

exposesReturnsTwice: false

legalized:       false

regBankSelected: false

selected:        false

tracksRegLiveness: true

registers:       

  - { id: 0, class: g8rc, preferred-register: '' }

  - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }

  - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }

  - { id: 3, class: crrc, preferred-register: '' }

  - { id: 4, class: g8rc, preferred-register: '' }

liveins:         

  - { reg: '%x3', virtual-reg: '%0' }

  - { reg: '%x4', virtual-reg: '%1' }

frameInfo:       

  isFrameAddressTaken: false

  isReturnAddressTaken: false

  hasStackMap:     false

  hasPatchPoint:   false

  stackSize:       0

  offsetAdjustment: 0

  maxAlignment:    0

  adjustsStack:    false

  hasCalls:        false

  stackProtector:  ''

  maxCallFrameSize: 4294967295

  hasOpaqueSPAdjustment: false

  hasVAStart:      false

  hasMustTailInVarArgFunc: false

  savePoint:       ''

  restorePoint:    ''

fixedStack:      

stack:           

constants:       

body:             |

  bb.0.entry:

    liveins: %x3, %x4

  

    %1 = COPY %x4

    %0 = LI8 200

    %2 = RLDICLo %0, 61, 3, implicit-def %cr0

    ; CHECK-NOT: ANDI

    ; CHECK-LATE-NOT: andi.

    %3 = COPY killed %cr0

    %4 = ISEL8 %1, %2, %3.sub_eq

    %x3 = COPY %4

    BLR8 implicit %lr8, implicit %rm, implicit %x3



...

---

name:            testRLDICLo3
@@ -4232,6 +4303,69 @@ body: | 
    %x3 = COPY %9

    BLR8 implicit %lr8, implicit %rm, implicit %x3



...

---

name:            testRLWINMo2

# CHECK-ALL: name: testRLWINMo2

alignment:       4

exposesReturnsTwice: false

legalized:       false

regBankSelected: false

selected:        false

tracksRegLiveness: true

registers:       

  - { id: 0, class: g8rc, preferred-register: '' }

  - { id: 1, class: g8rc, preferred-register: '' }

  - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }

  - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }

  - { id: 4, class: gprc, preferred-register: '' }

  - { id: 5, class: crrc, preferred-register: '' }

  - { id: 6, class: gprc, preferred-register: '' }

  - { id: 7, class: g8rc, preferred-register: '' }

  - { id: 8, class: g8rc, preferred-register: '' }

  - { id: 9, class: g8rc, preferred-register: '' }

liveins:         

  - { reg: '%x3', virtual-reg: '%0' }

  - { reg: '%x4', virtual-reg: '%1' }

frameInfo:       

  isFrameAddressTaken: false

  isReturnAddressTaken: false

  hasStackMap:     false

  hasPatchPoint:   false

  stackSize:       0

  offsetAdjustment: 0

  maxAlignment:    0

  adjustsStack:    false

  hasCalls:        false

  stackProtector:  ''

  maxCallFrameSize: 4294967295

  hasOpaqueSPAdjustment: false

  hasVAStart:      false

  hasMustTailInVarArgFunc: false

  savePoint:       ''

  restorePoint:    ''

fixedStack:      

stack:           

constants:       

body:             |

  bb.0.entry:

    liveins: %x3, %x4

  

    %1 = COPY %x4

    %0 = COPY %x3

    %2 = COPY %1.sub_32

    %3 = LI -22

    %4 = RLWINMo %3, 5, 24, 31, implicit-def %cr0

    ; CHECK-NOT: ANDI

    ; CHECK-LATE-NOT: andi.

    %5 = COPY killed %cr0

    %6 = ISEL %2, %3, %5.sub_eq

    %8 = IMPLICIT_DEF

    %7 = INSERT_SUBREG %8, killed %6, 1

    %9 = RLDICL killed %7, 0, 32

    %x3 = COPY %9

    BLR8 implicit %lr8, implicit %rm, implicit %x3



...

---

name:            testRLWINM8o