Commit 5c3569ba authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r238147: 

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r238147 | thomas.stellard | 2015-05-25 12:15:54 -0400 (Mon, 25 May 2015) | 4 lines

R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips

The src and dst register cannot be the same on chips with 16 lds banks.

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llvm-svn: 240285
parent bff8639e

llvm/lib/Target/R600/AMDGPU.td

+12 −2
Original line number Diff line number Diff line
@@ -121,6 +121,15 @@ def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>; 
def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;

def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;



class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <

      "ldsbankcount"#Value,

      "LDSBankCount",

      !cast<string>(Value),

      "The number of LDS banks per compute unit.">;



def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;

def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;



class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<

        "localmemorysize"#Value,

        "LocalMemorySize",
@@ -152,7 +161,7 @@ def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS", 


def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",

        [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,

         FeatureWavefrontSize64]>;

         FeatureWavefrontSize64, FeatureLDSBankCount32]>;



def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",

        [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
@@ -160,7 +169,8 @@ def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS", 


def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",

        [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,

         FeatureWavefrontSize64, FeatureFlatAddressSpace]>;

         FeatureWavefrontSize64, FeatureFlatAddressSpace,

         FeatureLDSBankCount32]>;



//===----------------------------------------------------------------------===//

llvm/lib/Target/R600/AMDGPUSubtarget.cpp

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS, 
      EnablePromoteAlloca(false), EnableIfCvt(true),

      EnableLoadStoreOpt(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),

      EnableVGPRSpilling(false),SGPRInitBug(false),

      LDSBankCount(0),

      DL(computeDataLayout(initializeSubtargetDependencies(GPU, FS))),

      FrameLowering(TargetFrameLowering::StackGrowsUp,

                    64 * 16, // Maximum stack alignment (long16)

llvm/lib/Target/R600/AMDGPUSubtarget.h

+5 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ private: 
  int LocalMemorySize;

  bool EnableVGPRSpilling;

  bool SGPRInitBug;

  int LDSBankCount;



  const DataLayout DL;

  AMDGPUFrameLowering FrameLowering;
@@ -212,6 +213,10 @@ public: 
    return SGPRInitBug;

  }



  int getLDSBankCount() const {

    return LDSBankCount;

  }



  unsigned getAmdKernelCodeChipID() const;



  bool enableMachineScheduler() const override {

llvm/lib/Target/R600/Processors.td

+14 −5
Original line number Diff line number Diff line
@@ -99,15 +99,24 @@ def : ProcessorModel<"hainan", SIQuarterSpeedModel, [FeatureSouthernIslands]>; 
// Sea Islands

//===----------------------------------------------------------------------===//



def : ProcessorModel<"bonaire",    SIQuarterSpeedModel, [FeatureSeaIslands]>;

def : ProcessorModel<"bonaire",    SIQuarterSpeedModel,

  [FeatureSeaIslands, FeatureLDSBankCount32]

>;



def : ProcessorModel<"kabini",     SIQuarterSpeedModel, [FeatureSeaIslands]>;

def : ProcessorModel<"kabini",     SIQuarterSpeedModel,

  [FeatureSeaIslands, FeatureLDSBankCount16]

>;



def : ProcessorModel<"kaveri",     SIQuarterSpeedModel, [FeatureSeaIslands]>;

def : ProcessorModel<"kaveri",     SIQuarterSpeedModel,

  [FeatureSeaIslands, FeatureLDSBankCount32]

>;



def : ProcessorModel<"hawaii",     SIFullSpeedModel, [FeatureSeaIslands]>;

def : ProcessorModel<"hawaii", SIFullSpeedModel,

  [FeatureSeaIslands, FeatureLDSBankCount32]

>;



def : ProcessorModel<"mullins",    SIQuarterSpeedModel, [FeatureSeaIslands]>;

def : ProcessorModel<"mullins",    SIQuarterSpeedModel,

  [FeatureSeaIslands, FeatureLDSBankCount16]>;



//===----------------------------------------------------------------------===//

// Volcanic Islands

llvm/lib/Target/R600/SIInstructions.td

+34 −5
Original line number Diff line number Diff line
@@ -40,6 +40,9 @@ def isVI : Predicate < 


def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">;



def has16BankLDS : Predicate<"Subtarget.getLDSBankCount() == 16">;

def has32BankLDS : Predicate<"Subtarget.getLDSBankCount() == 32">;



def SWaitMatchClass : AsmOperandClass {

  let Name = "SWaitCnt";

  let RenderMethod = "addImmOperands";
@@ -1376,12 +1379,26 @@ defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64", 
//===----------------------------------------------------------------------===//



// FIXME: Specify SchedRW for VINTRP insturctions.

defm V_INTERP_P1_F32 : VINTRP_m <



multiclass V_INTERP_P1_F32_m : VINTRP_m <

  0x00000000,

  (outs VGPR_32:$dst),

  (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),

  "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [$m0]",

  "$m0">;

  "$m0"

>;



let OtherPredicates = [has32BankLDS] in {



defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;



} // End OtherPredicates = [has32BankLDS]



let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst" in {



defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;



} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst"



defm V_INTERP_P2_F32 : VINTRP_m <

  0x00000001,
@@ -2672,14 +2689,26 @@ def : Pat < 
  (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, (S_MOV_B32 $params))

>;



def : Pat <

class FSInterpPat <Instruction P1> : Pat <

  (int_SI_fs_interp imm:$attr_chan, imm:$attr, i32:$params, v2i32:$ij),

  (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),

  (V_INTERP_P2_F32 (P1 (EXTRACT_SUBREG v2i32:$ij, sub0),

                                    imm:$attr_chan, imm:$attr, (S_MOV_B32 $params)),

                   (EXTRACT_SUBREG $ij, sub1),

                   imm:$attr_chan, imm:$attr, (S_MOV_B32 $params))

>;



let Predicates = [has32BankLDS] in {



def : FSInterpPat<V_INTERP_P1_F32>;



} // EndPredicates = [has32BankLDS]



let Predicates = [has16BankLDS] in {



def : FSInterpPat<V_INTERP_P1_F32_16bank>;



} // End Predicates = [has32BankLDS]



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/********** Intrinsic Patterns **********/

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