Commit 59108aca authored by Hans Wennborg's avatar Hans Wennborg
Browse files

[AArch64][GlobalISel] Support G_INSERT/G_EXTRACT of types < s32 bits. 

These are needed for operations on fp16 types in a later patch.

This also re-instates the test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
test that was deleted which depended on this patch.

(See PR36345.)

llvm-svn: 325669
parent 0c14c942

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

+20 −3
Original line number Diff line number Diff line
@@ -839,15 +839,23 @@ bool AArch64InstructionSelector::select(MachineInstr &I, 
  }

  case TargetOpcode::G_EXTRACT: {

    LLT SrcTy = MRI.getType(I.getOperand(1).getReg());

    LLT DstTy = MRI.getType(I.getOperand(0).getReg());

    unsigned SrcSize = SrcTy.getSizeInBits();

    // Larger extracts are vectors, same-size extracts should be something else

    // by now (either split up or simplified to a COPY).

    if (SrcTy.getSizeInBits() > 64 || Ty.getSizeInBits() > 32)

      return false;



    I.setDesc(TII.get(AArch64::UBFMXri));

    I.setDesc(TII.get(SrcSize == 64 ? AArch64::UBFMXri : AArch64::UBFMWri));

    MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() +

                                      Ty.getSizeInBits() - 1);



    if (SrcSize < 64) {

      assert(SrcSize == 32 && DstTy.getSizeInBits() == 16 &&

             "unexpected G_EXTRACT types");

      return constrainSelectedInstRegOperands(I, TII, TRI, RBI);

    }



    unsigned DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));

    BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(),

            TII.get(AArch64::COPY))
@@ -862,17 +870,26 @@ bool AArch64InstructionSelector::select(MachineInstr &I, 


  case TargetOpcode::G_INSERT: {

    LLT SrcTy = MRI.getType(I.getOperand(2).getReg());

    LLT DstTy = MRI.getType(I.getOperand(0).getReg());

    unsigned DstSize = DstTy.getSizeInBits();

    (void)DstSize;

    // Larger inserts are vectors, same-size ones should be something else by

    // now (split up or turned into COPYs).

    if (Ty.getSizeInBits() > 64 || SrcTy.getSizeInBits() > 32)

      return false;



    I.setDesc(TII.get(AArch64::BFMXri));

    I.setDesc(TII.get(DstSize == 64 ? AArch64::BFMXri : AArch64::BFMWri));

    unsigned LSB = I.getOperand(3).getImm();

    unsigned Width = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();

    I.getOperand(3).setImm((64 - LSB) % 64);

    I.getOperand(3).setImm((DstSize - LSB) % DstSize);

    MachineInstrBuilder(MF, I).addImm(Width - 1);



    if (DstSize < 64) {

      assert(DstSize == 32 && SrcTy.getSizeInBits() == 16 &&

             "unexpected G_INSERT types");

      return constrainSelectedInstRegOperands(I, TII, TRI, RBI);

    }



    unsigned SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64));

    BuildMI(MBB, I.getIterator(), I.getDebugLoc(),

            TII.get(AArch64::SUBREG_TO_REG))

llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir

0 → 100644
+131 −0
Original line number Diff line number Diff line 
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -mtriple=aarch64-unknown-unknown -o - -global-isel -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s



# PR36345

--- |

  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"

  target triple = "aarch64-arm-none-eabi"



  ; Function Attrs: noinline nounwind optnone

  define void @fp16_to_gpr([2 x half], [2 x half]* %addr) {

    ret void

  }



  define void @gpr_to_fp16() {

    ret void

  }



  define void @gpr_to_fp16_physreg() {

    ret void

  }

...

---

name:            fp16_to_gpr

alignment:       2

legalized:       true

regBankSelected: true

tracksRegLiveness: true

registers:

  - { id: 0, class: gpr }

  - { id: 1, class: fpr }

  - { id: 2, class: fpr }

  - { id: 3, class: gpr }

  - { id: 4, class: gpr }

  - { id: 5, class: gpr }

  - { id: 6, class: gpr }

  - { id: 7, class: gpr }

  - { id: 8, class: gpr }

  - { id: 9, class: gpr }

  - { id: 10, class: gpr }

  - { id: 11, class: gpr }

  - { id: 12, class: gpr }

body:             |

  bb.1 (%ir-block.1):

    liveins: %h0, %h1, %x0



    ; CHECK-LABEL: name: fp16_to_gpr

    ; CHECK: liveins: %h0, %h1, %x0

    ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0

    ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY %h1

    ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF

    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub

    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]

    ; CHECK: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY2]], 0, 15

    ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub

    ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG1]]

    ; CHECK: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY3]], 16, 15

    ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[BFMWri1]]

    ; CHECK: [[COPY5:%[0-9]+]]:gpr64sp = COPY %x0

    ; CHECK: STRWui [[COPY4]], [[COPY5]], 0 :: (store 4 into %ir.addr, align 2)

    ; CHECK: RET_ReallyLR

    %1:fpr(s16) = COPY %h0

    %2:fpr(s16) = COPY %h1

    %3:gpr(s32) = G_IMPLICIT_DEF

    %11:gpr(s16) = COPY %1(s16)

    %4:gpr(s32) = G_INSERT %3, %11(s16), 0

    %12:gpr(s16) = COPY %2(s16)

    %5:gpr(s32) = G_INSERT %4, %12(s16), 16

    %0:gpr(s32) = COPY %5(s32)

    %6:gpr(p0) = COPY %x0

    G_STORE %0(s32), %6(p0) :: (store 4 into %ir.addr, align 2)

    RET_ReallyLR



...



---

name:            gpr_to_fp16

alignment:       2

legalized:       true

regBankSelected: true

tracksRegLiveness: true

registers:

  - { id: 0, class: gpr }

  - { id: 1, class: gpr }

  - { id: 2, class: fpr }

body:             |

  bb.1 (%ir-block.0):

    liveins: %w0



    ; CHECK-LABEL: name: gpr_to_fp16

    ; CHECK: liveins: %w0

    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0

    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]

    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[COPY1]]

    ; CHECK: [[COPY3:%[0-9]+]]:fpr16 = COPY [[COPY2]].hsub

    ; CHECK: [[COPY4:%[0-9]+]]:fpr16 = COPY [[COPY3]]

    ; CHECK: %h0 = COPY [[COPY4]]

    ; CHECK: RET_ReallyLR implicit %h0

    %0:gpr(s32) = COPY %w0

    %1:gpr(s16) = G_TRUNC %0(s32)

    %2:fpr(s16) = COPY %1(s16)

    %h0 = COPY %2(s16)

    RET_ReallyLR implicit %h0



...

---

name:            gpr_to_fp16_physreg

alignment:       2

legalized:       true

regBankSelected: true

tracksRegLiveness: true

registers:

  - { id: 0, class: gpr }

  - { id: 1, class: gpr }

body:             |

  bb.1 (%ir-block.0):

    liveins: %w0



    ; CHECK-LABEL: name: gpr_to_fp16_physreg

    ; CHECK: liveins: %w0

    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0

    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]

    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[COPY1]]

    ; CHECK: [[COPY3:%[0-9]+]]:fpr16 = COPY [[COPY2]].hsub

    ; CHECK: %h0 = COPY [[COPY3]]

    ; CHECK: RET_ReallyLR implicit %h0

    %0:gpr(s32) = COPY %w0

    %1:gpr(s16) = G_TRUNC %0(s32)

    %h0 = COPY %1(s16)

    RET_ReallyLR implicit %h0



...

llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir

+75 −13
Original line number Diff line number Diff line 
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s



---

# CHECK-LABEL: name: insert_gprs

name:            insert_gprs

name:            insert_gprx

legalized:       true

regBankSelected: true
@@ -10,26 +10,56 @@ body: | 
  bb.0:

    liveins: %x0



    ; CHECK-LABEL: name: insert_gprx

    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0

    ; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF

    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32

    ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG]], 0, 31

    ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32

    ; CHECK: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 51, 31

    ; CHECK: %x0 = COPY [[BFMXri]]

    ; CHECK: %x1 = COPY [[BFMXri1]]

    %0:gpr(s32) = COPY %w0



    %1:gpr(s64) = G_IMPLICIT_DEF



    ; CHECK:  body:

    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32

    ; CHECK: %2:gpr64 = BFMXri %1, [[TMP]], 0, 31

    %2:gpr(s64) = G_INSERT %1, %0, 0



    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32

    ; CHECK: %3:gpr64 = BFMXri %1, [[TMP]], 51, 31

    %3:gpr(s64) = G_INSERT %1, %0, 13



    %x0 = COPY %2

    %x1 = COPY %3

...



---

name:            insert_gprw

legalized:       true

regBankSelected: true



body:             |

  bb.0:

    liveins: %w0, %w1

    ; CHECK-LABEL: name: insert_gprw

    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0

    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]

    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY]]

    ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF

    ; CHECK: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY1]], 0, 15

    ; CHECK: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY2]], 16, 15

    ; CHECK: [[COPY3:%[0-9]+]]:gpr32all = COPY [[BFMWri1]]

    ; CHECK: %w0 = COPY [[COPY3]]

    %1:gpr(s32) = COPY %w0

    %2:gpr(s32) = COPY %w1

    %3:gpr(s16) = G_TRUNC %1(s32)

    %4:gpr(s16) = G_TRUNC %1(s32)

    %5:gpr(s32) = G_IMPLICIT_DEF

    %6:gpr(s32) = G_INSERT %5, %3(s16), 0

    %7:gpr(s32) = G_INSERT %6, %4(s16), 16

    %0:gpr(s32) = COPY %7(s32)

    %w0 = COPY %0

...



---

# CHECK-LABEL: name: extract_gprs

name:            extract_gprs

legalized:       true

regBankSelected: true
@@ -38,17 +68,49 @@ body: | 
  bb.0:

    liveins: %x0



    ; CHECK-LABEL: name: extract_gprs

    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0

    ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 0, 31

    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[UBFMXri]].sub_32

    ; CHECK: [[UBFMXri1:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 13, 44

    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[UBFMXri1]].sub_32

    ; CHECK: %w0 = COPY [[COPY1]]

    ; CHECK: %w1 = COPY [[COPY2]]

    %0:gpr(s64) = COPY %x0



    ; CHECK:  body:

    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = UBFMXri %0, 0, 31

    ; CHECK: %1:gpr32 = COPY [[TMP]].sub_32

    %1:gpr(s32) = G_EXTRACT %0, 0



    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = UBFMXri %0, 13, 44

    ; CHECK: %2:gpr32 = COPY [[TMP]].sub_32

    %2:gpr(s32) = G_EXTRACT %0, 13



    %w0 = COPY %1

    %w1 = COPY %2

...



---

name:            extract_gprw

legalized:       true

regBankSelected: true



body:             |

  bb.0:

    liveins: %w0



    ; CHECK-LABEL: name: extract_gprw

    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0

    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15

    ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 15, 30

    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[UBFMWri]]

    ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub

    ; CHECK: %h0 = COPY [[COPY2]]

    ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[UBFMWri1]]

    ; CHECK: [[COPY4:%[0-9]+]]:fpr16 = COPY [[COPY3]].hsub

    ; CHECK: %h1 = COPY [[COPY4]]

    %0:gpr(s32) = COPY %w0



    %1:gpr(s16) = G_EXTRACT %0, 0



    %2:gpr(s16) = G_EXTRACT %0, 15



    %h0 = COPY %1

    %h1 = COPY %2

...