Commit 3cec2c1d authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r329761: 

------------------------------------------------------------------------
r329761 | gberry | 2018-04-10 14:43:03 -0700 (Tue, 10 Apr 2018) | 13 lines

[AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.

Summary:
When inserting MOVs to avoid Falkor HWPF collisions, the non-base
register operand of load instructions (e.g. a register offset) was not
being considered live, so it could potentially have been used as a
scratch register, clobbering the actual offset value.

Reviewers: mcrosier

Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45502
------------------------------------------------------------------------

llvm-svn: 330209
parent 64734c43

llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

+18 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
#include "llvm/Pass.h"

#include "llvm/Support/Casting.h"

#include "llvm/Support/Debug.h"

#include "llvm/Support/DebugCounter.h"

#include "llvm/Support/raw_ostream.h"

#include <cassert>

#include <iterator>
@@ -60,6 +61,8 @@ STATISTIC(NumCollisionsAvoided, 
          "Number of HW prefetch tag collisions avoided");

STATISTIC(NumCollisionsNotAvoided,

          "Number of HW prefetch tag collisions not avoided due to lack of regsiters");

DEBUG_COUNTER(FixCounter, "falkor-hwpf",

              "Controls which tag collisions are avoided");



namespace {
@@ -729,6 +732,21 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) { 
      bool Fixed = false;

      DEBUG(dbgs() << "Attempting to fix tag collision: " << MI);



      if (!DebugCounter::shouldExecute(FixCounter)) {

        DEBUG(dbgs() << "Skipping fix due to debug counter:\n  " << MI);

        continue;

      }



      // Add the non-base registers of MI as live so we don't use them as

      // scratch registers.

      for (unsigned OpI = 0, OpE = MI.getNumOperands(); OpI < OpE; ++OpI) {

        if (OpI == static_cast<unsigned>(LdI.BaseRegIdx))

          continue;

        MachineOperand &MO = MI.getOperand(OpI);

        if (MO.isReg() && MO.readsReg())

          LR.addReg(MO.getReg());

      }



      for (unsigned ScratchReg : AArch64::GPR64RegClass) {

        if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg))

          continue;

llvm/test/CodeGen/AArch64/falkor-hwpf-fix.mir

+25 −0
Original line number Diff line number Diff line
@@ -353,3 +353,28 @@ body: | 
  bb.1:

    RET_ReallyLR

...

---

# Check that non-base registers are considered live when finding a

# scratch register by making sure we don't use %x2 for the scratch

# register for the inserted ORRXrs.

# CHECK-LABEL: name: hwpf_offreg

# CHECK: %x3 = ORRXrs %xzr, %x1, 0

# CHECK: %w10 = LDRWroX %x3, %x2, 0, 0

name:            hwpf_offreg

tracksRegLiveness: true

body: |

  bb.0:

    liveins: %w0, %x1, %x2, %x17, %x18



    %w10 = LDRWroX %x1, %x2, 0, 0 :: ("aarch64-strided-access" load 4)



    %x2 = ORRXrs %xzr, %x10, 0

    %w26 = LDRWroX %x1, %x2, 0, 0



    %w0 = SUBWri %w0, 1, 0

    %wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv

    Bcc 9, %bb.0, implicit %nzcv



  bb.1:

    RET_ReallyLR

...