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- 04 Oct, 2021 1 commit
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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- 23 Feb, 2021 1 commit
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Nguyen, Thien Minh authored
Tyler reported a case where the circuit after optimized used the qreg name 'q' rather than a random buffer name that qcor assigned. Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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- 23 Oct, 2020 1 commit
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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- 29 Jul, 2020 1 commit
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Nguyen, Thien Minh authored
The gates were inserted in reverse order :( Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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- 21 Jul, 2020 3 commits
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
There is some potential compatibility issues with external linkage. Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
- CZ gate def: required bits = 2. - KAK: fixed numerical errors related to tolerance, added validation checks for simplified circuits. - Gate merge: fixed endians, added validation. Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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- 16 Jul, 2020 3 commits
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Nguyen, Thien Minh authored
Optimized block == rest of circuit. Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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- 15 Jul, 2020 3 commits
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
Used it in the optimization routine. Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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