Commits · 7b7d10bfefdf5f1ded5fc417bb9250e185be98ea · ORNL Quantum Computing Institute / xacc

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04 Oct, 2021 1 commit
- Added some missing header include clauses · 9fbb9607
  Nguyen, Thien Minh authored Oct 04, 2021
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Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
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  9fbb9607
23 Feb, 2021 1 commit

Fixed a bug when the gate merge optimizer didn't persist the buffer name · dd59aaee

Nguyen, Thien Minh authored Feb 23, 2021



Tyler reported a case where the circuit after optimized used the qreg name 'q' rather than a random buffer name that qcor assigned.
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

dd59aaee

26 Oct, 2020 1 commit

Fixed a nasty typo in Kak implementation · 352a4efd

Nguyen, Thien Minh authored Oct 26, 2020

Typo in IR construction but not in validation code hence can escape all the asserts in Kak.

Updated the gate merging unit test which uses KAK to be more rigorous in catching these potential bugs.
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

352a4efd

23 Oct, 2020 1 commit
- Fixed gate merge optimization when there are nested composites · bef6aa79
  Nguyen, Thien Minh authored Oct 23, 2020
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Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
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  bef6aa79
29 Jul, 2020 1 commit
- Fixed gate merge bug during circuit rewrite · bfa3828e
  Nguyen, Thien Minh authored Jul 29, 2020
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The gates were inserted in reverse order :(
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
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  bfa3828e
21 Jul, 2020 3 commits

Forgot to re-transpose the matrix for validation · ce9f736a
Nguyen, Thien Minh authored Jul 21, 2020
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Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
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ce9f736a

Used std::vector in Heterogeneous map in gate merge procedure · bf32390f

Nguyen, Thien Minh authored Jul 21, 2020



There is some potential compatibility issues with external linkage.
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

bf32390f

Fixed GateMerge, KAK, gate def · 4ea24ac6

Nguyen, Thien Minh authored Jul 21, 2020



- CZ gate def: required bits = 2.

- KAK: fixed numerical errors related to tolerance, added validation checks for simplified circuits.

- Gate merge: fixed endians, added validation.
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

4ea24ac6

16 Jul, 2020 4 commits
- Fixed an edge case · 60c35f1c
  Nguyen, Thien Minh authored Jul 16, 2020
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Optimized block == rest of circuit.
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
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  60c35f1c
- Implemented two-qubit block merging · 6213a433
  Nguyen, Thien Minh authored Jul 16, 2020
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Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
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  6213a433
- Added a kitchen-sink test · 0999695f
  Nguyen, Thien Minh authored Jul 16, 2020
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Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
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  0999695f
- Simplified the gate scan routine · 685377e5
  Nguyen, Thien Minh authored Jul 16, 2020
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Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
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  685377e5
15 Jul, 2020 3 commits
- Completed single-qubit gate merge optimization pass · 86fafddd
  Nguyen, Thien Minh authored Jul 15, 2020
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Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
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  86fafddd
- Refactored the ZYZ decomposition inside KAK into a separate circuit · 20edde54
  Nguyen, Thien Minh authored Jul 15, 2020
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Used it in the optimization routine.
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
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  20edde54
- Initial set-up for some additional circuit optimization routines · d9e8194d
  Nguyen, Thien Minh authored Jul 15, 2020
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Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>
```
  d9e8194d