GitLab

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Add some instructions for common ion trap native gates

AcceleratorBuffer: Use exp-val-z extra info for getExpectationValueZ() if present

Unconditonally return exp-val-z from AcceleratorBuffer extra info as
getExpectationValueZ() if exists. If we have a more precise result at
hand, why not use it instead of calculating a less precise answer?
Signed-off-by: Austin Adams <aja@gatech.edu>

Not sure if users would use these, but they are useful in
IRTransformations in the GTRI testbed backend.

Definitions are from the Methods section of the following paper:
https://www.nature.com/articles/nature18648

Signed-off-by: Austin Adams <aja@gatech.edu>

qpp Accelerator: Check for post-measure gates more accurately

As a result of XACC IR being serialized, it's possible to have gates
follow Measure instructions without the circuit truly having
post-measure gates. For example:

    H 0
    Measure 0
    H 1
    Measure 1

In cases like that, the current QppAccelerator decides it cannot
simulate the circuit once and repeatedly sample the resulting state
vector to simulate "runs." That is an overzealous judgment, since none
of the gates that follow the Measure instructions actually depend on the
results of measurements.

So instead, in the QppAccelerator logic detecting post-measurement
gates, track which qubits have been measured, and only report
post-measurement gates if it sees a gate operating on a qubit with an
earlier Measure instruction.
Signed-off-by: Austin Adams <aja@gatech.edu>

Signed-off-by: Alex McCaskey <mccaskeyaj@ornl.gov>

Add placement option to QAOA

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Alex McCaskey <mccaskeyaj@ornl.gov>

Signed-off-by: Alex McCaskey <mccaskeyaj@ornl.gov>

Signed-off-by: Alex McCaskey <mccaskeyaj@ornl.gov>

Signed-off-by: Alex McCaskey <mccaskeyaj@ornl.gov>

Signed-off-by: Alex McCaskey <mccaskeyaj@ornl.gov>

Support IfStmt to OpenQASM2 generation

Note: Aer can simulate conditional (bfunc) in the QObj and XACC translate IfStmt to bfunc appropriately.
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Testing non-conventional gate set.
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

The procedure was not properly taking into account non-IBM gateset, i.e., 2-q gates may not be CNOT.
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Consider SWAPs in swap-shortest-path

Remove SWAP gates from the two-qubit gate whitelist for Staq placement
also modified in f1eedf04. Otherwise, Swap instructions between
non-adjacent qubits can slip through the swap-shortest-path
IRTransformation. An example of this would be the QCOR qft() routine,
which can generate a Swap between far-away qubits at the end.

Combined with f1eedf04

, fixes ORNL-QCI/qcor#199.
Signed-off-by: Austin Adams <aja@gatech.edu>

Creg can be larger than qreg (e.g., IQPE) and need to handle explicit Measure assignment.

Tested by: validating with Honeywell APIVAL
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

XACCToStaqOpenQASM visitor to handle IfStmt (currently empty impl)
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Alex McCaskey <mccaskeyaj@ornl.gov>

Relax a QAOA test condition for CI stability

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

First pass of implementing Accelerator::getNativeCode

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Handle single-cbit conditional for OpenQASM code gen.
Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>

Signed-off-by: Alex McCaskey <mccaskeyaj@ornl.gov>