This is the optimization routine #4 in https://arxiv.org/pdf/1710.07345.pdf



Basically, it's a 3-step process:

- Identify the subcircuit (only contains X, CNOT, or Rz gates)
(this includes circuit pruning)

- Find the boolean polynomials for each Rz gate.

- Merge those Rz gates that have the same boolean polynomial.

Also, added unit tests to check the execution.

Fixed IRToGraph visitor to handle Identity gate and to output error if it encounters an unknown gate. This prevents it from silently ignoring those unknown gates (could create mismatches between graph and circuit views)

Signed-off-by: Thien Nguyen <nguyentm@ornl.gov>