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- 27 Oct, 2021 2 commits
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
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- 26 Oct, 2021 2 commits
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Mccaskey, Alex authored
Squashing all work to implement region-based OpenQASM3 modifier scope block
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- 22 Oct, 2021 1 commit
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Nguyen, Thien Minh authored
Descriptions: modifier (inv, ctrl, pow) Ops in the dialect has an associated (single-block) region. These ops have proper data flow tracking, i.e., subsequence quantum ops will take output of these modifier ops, not the wrapped instructions. The connection b/w the region-wrapped code and the op returns are handled by the quantum yield op (terminator for these modifier ops). Lowering/optimization: - If no optimization is required, these ops will be lowered to runtime (start/end) functions, identical to the current behavior. I need to separate part of this lowering (involves inlining the wrapped region into the parent region) to a individual pass, executed before the quantum-to-llvm dialect conversion b/c of some weird interactions with other dialect conversion patterns (e.g., qvs conversion) and type conversion. In some sense, when inlining the body, we are creating (cloning/copying) new MLIR Ops in the quantum dialect, so it needs to be executed before the whole quantum-to-llvm pass. - If optimization is turned on: when possible (e.g., the wrapped code only contains qvs ops), it will resolve the modifier at compile time: reverse gates for inv, derive the ctr-gates, rewrite pow->for loops. Modifiers that cannot be optimized will remain and be handled by the lowering step above. Added tests. There is an edge case that this doesn't cover is compute-action. I retain the existing behavior by directly calling runtime functions. Hence, the SSA tracking in this use case is not reliable for optimization. Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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- 19 Oct, 2021 2 commits
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Thien Nguyen authored
Added <optional> header include
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Nguyen, Thien Minh authored
Required for gcc11+ due to header file re-structuring. Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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- 13 Oct, 2021 2 commits
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Mccaskey, Alex authored
Added compiler switch to select kernel's autograd method
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Nguyen, Thien Minh authored
Fix a copy and paste bug in gradient method service registry lookup (backward looked for forward impl...) Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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- 12 Oct, 2021 4 commits
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Mccaskey, Alex authored
Fixed Clang build
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Mccaskey, Alex authored
Signed-off-by:
Alex McCaskey <mccaskeyaj@ornl.gov>
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Mccaskey, Alex authored
Signed-off-by:
Alex McCaskey <mccaskeyaj@ornl.gov>
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- 11 Oct, 2021 4 commits
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Thien Nguyen authored
Fixed a bug in ScopedSymbolTable::invalidate_qubit_extracts
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Nguyen, Thien Minh authored
Must check the optional return before trying to deref. This shows up in one of the demos whereby the QASM3 source only contains a kernel **definition** and the size of qreg argument is unknown. Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Thien Nguyen authored
Fixed a typo in compile command comment of a demo example Comment changes only.
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Nguyen, Thien Minh authored
the file name is iqft.qasm. Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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- 07 Oct, 2021 1 commit
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Mccaskey, Alex authored
Signed-off-by:
Alex McCaskey <mccaskeyaj@ornl.gov>
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- 24 Sep, 2021 1 commit
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Mccaskey, Alex authored
Signed-off-by:
Alex McCaskey <mccaskeyaj@ornl.gov>
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- 23 Sep, 2021 1 commit
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Mccaskey, Alex authored
Signed-off-by:
Alex McCaskey <mccaskeyaj@ornl.gov>
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- 22 Sep, 2021 8 commits
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Mccaskey, Alex authored
Added HPC demo for random circuit (TNQVM) and adder circuit (DM-SIM )
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Nguyen, Thien Minh authored
To minimize the risk of Summit unavailability, TNQVM/ExaTN demo will be based on Andes. DM-Sim on Summit: 1GPU demo on login node, multi-GPU live demo if interactive session available. Otherwise, just do a job submission... Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Mccaskey, Alex authored
Signed-off-by:
Alex McCaskey <mccaskeyaj@ornl.gov>
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Mccaskey, Alex authored
Signed-off-by:
Alex McCaskey <mccaskeyaj@ornl.gov>
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Mccaskey, Alex authored
Signed-off-by:
Alex McCaskey <mccaskeyaj@ornl.gov>
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Mccaskey, Alex authored
Signed-off-by:
Alex McCaskey <mccaskeyaj@ornl.gov>
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- 21 Sep, 2021 10 commits
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Mccaskey, Alex authored
Added QASM3 adder example
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
The code to detect the type is correct in detecting Memref type or not but the below code **always** does a LoadOp. In the case of non-memref type current value, it's causing seg-fault in LLVM internal code.... Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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https://github.com/ORNL-QCI/qcor/issues/226Nguyen, Thien Minh authored
While having an LLVM build with assert on, fixing those asserts: - extraneous eraseOp - unused variable which is actually an error (cannot get Int/Float bit width of a memref type) Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
On Summit, looks like the Clang-CSP was not able to link properly at the final linking phase. So just having an option to use the system compiler if needed. Signed-off-by:
Thien Nguyen <nguyentm@ornl.gov>
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Nguyen, Thien Minh authored
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- 20 Sep, 2021 2 commits
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Mccaskey, Alex authored
Paramaterized gate definition segfault fixed
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Omar Ibrahim authored
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