Commit aa204568 authored by Nguyen, Thien Minh's avatar Nguyen, Thien Minh
Browse files

Fixed a lowering bug whereby the bit-width narrowing was not properly handled 



Signed-off-by: default avatarThien Nguyen <nguyentm@ornl.gov>
parent 3c804049

mlir/parsers/qasm3/examples/adder.qasm

+3 −5
Original line number Diff line number Diff line
@@ -62,11 +62,9 @@ qubit a[8]; 
qubit b[8];

qubit cout;

bit ans[9];



// FIXME: left shift casting to handle different type:

// e.g. i8 vs. i64 (shift value)

uint[64] a_in = 1;  

uint[64] b_in = 15; 

// Input values:

uint[8] a_in = 1;  

uint[8] b_in = 15; 



for i in [0:8] {

  // FIXME: not able to do this inline....

mlir/transforms/lowering/InstOpLowering.cpp

+8 −1
Original line number Diff line number Diff line
@@ -171,7 +171,14 @@ LogicalResult IntegerCastOpLowering::matchAndRewrite( 
  mlir::IntegerType type = to_be_cast.getType().cast<mlir::IntegerType>();

  auto cast_op = rewriter.create<LLVM::DialectCastOp>(

      loc, rewriter.getIntegerType(type.getWidth(), false), to_be_cast);

  if (resultCastOp.getType().getWidth() < type.getWidth()) {

    auto trunc_op = rewriter.create<LLVM::TruncOp>(loc, resultCastOp.getType(),

                                                   cast_op.res());

    rewriter.replaceOp(op, trunc_op.res());

  } else {

    rewriter.replaceOp(op, cast_op.res());

  }



  return success();

}

}  // namespace qcor
 
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