Commit b8fe1746 authored by Weijia Wang's avatar Weijia Wang
Browse files

spike: unpin gcc12

parent f893cc7d
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+9 −1
Original line number Diff line number Diff line
{ lib, stdenv, fetchFromGitHub, dtc, pkgsCross }:
{ lib, stdenv, fetchFromGitHub, fetchpatch, dtc, pkgsCross }:

stdenv.mkDerivation rec {
  pname = "spike";
@@ -11,6 +11,14 @@ stdenv.mkDerivation rec {
    sha256 = "sha256-4D2Fezej0ioOOupw3kgMT5VLs+/jXQjwvek6v0AVMzI=";
  };

  patches = [
    (fetchpatch {
      name = "fesvr-fix-compilation-with-gcc-13.patch";
      url = "https://github.com/riscv-software-src/riscv-isa-sim/commit/0a7bb5403d0290cea8b2356179d92e4c61ffd51d.patch";
      hash = "sha256-JUMTbGawvLkoOWKkruzLzUFQytVR3wqTlGu/eegRFEE=";
    })
  ];

  nativeBuildInputs = [ dtc ];
  enableParallelBuilding = true;

+1 −1
Original line number Diff line number Diff line
@@ -35089,7 +35089,7 @@ with pkgs;
  spice-vdagent = callPackage ../applications/virtualization/spice-vdagent { };
  spike = pin-to-gcc12-if-gcc13 (callPackage ../applications/virtualization/spike { });
  spike = callPackage ../applications/virtualization/spike { };
  tensorman = callPackage ../tools/misc/tensorman { };