Unverified Commit 87cb6e70 authored by Aleksana's avatar Aleksana Committed by GitHub
Browse files

Merge pull request #326966 from hzeller/feature-20240713-rename-verilog-to-iverilog 

verilog: rename to actual name iverilog
parents 320b9df8 61f0a17d

pkgs/applications/science/electronics/vhd2vl/default.nix

+2 −2
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
, fetchFromGitHub

, bison

, flex

, verilog

, iverilog

, which

}:
@@ -25,7 +25,7 @@ stdenv.mkDerivation rec { 
  ];



  buildInputs = [

    verilog

    iverilog

  ];



  # the "translate" target both (a) builds the software and (b) runs

pkgs/development/compilers/bluespec/default.nix

+2 −2
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
, zlib

, ghc

, gmp-static

, verilog

, iverilog

, asciidoctor

, texliveFull

, which
@@ -108,7 +108,7 @@ in stdenv.mkDerivation rec { 


  nativeCheckInputs = [

    gmp-static

    verilog

    iverilog

  ];



  checkTarget = "check-smoke"; # this is the shortest check but "check-suite" tests much more

pkgs/development/compilers/yosys/default.nix

+2 −2
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
, readline

, symlinkJoin

, tcl

, verilog

, iverilog

, zlib

, yosys

, yosys-bluespec
@@ -147,7 +147,7 @@ in stdenv.mkDerivation (finalAttrs: { 


  checkTarget = "test";

  doCheck = true;

  nativeCheckInputs = [ verilog ];

  nativeCheckInputs = [ iverilog ];



  setupHook = ./setup-hook.sh;

pkgs/development/python-modules/cocotb/default.nix

+2 −2
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ 
  find-libpython,

  pytestCheckHook,

  swig,

  verilog,

  iverilog,

  ghdl,

}:
@@ -65,7 +65,7 @@ buildPythonPackage rec { 
    cocotb-bus

    pytestCheckHook

    swig

    verilog

    iverilog

    ghdl

  ];

  preCheck = ''