Unverified Commit 03ad8569 authored by Jack Leightcap's avatar Jack Leightcap
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verilog-12.0: temp disable regression test suite 



Signed-off-by: default avatarJack Leightcap <jack@leightcap.com>
parent e9766716

pkgs/applications/science/electronics/verilog/default.nix

+6 −1
Original line number Diff line number Diff line
@@ -44,8 +44,13 @@ stdenv.mkDerivation rec { 


  enableParallelBuilding = true;



  # NOTE(jleightcap): the `make check` target only runs a "Hello, World"-esque sanity check.

  # the tests in the doInstallCheck phase run a full regression test suite.

  # however, these tests currently fail upstream on aarch64

  # (see https://github.com/steveicarus/iverilog/issues/917)

  # so disable the full suite for now.

  doCheck = true;

  doInstallCheck = true;

  doInstallCheck = false;



  nativeInstallCheckInputs = [

    perl