Loading lib/systems/architectures.nix +4 −0 Original line number Diff line number Diff line Loading @@ -26,6 +26,8 @@ rec { cooperlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; tigerlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; alderlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ]; sapphirerapids = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; emeraldrapids = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; # x86_64 AMD btver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ]; btver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ]; Loading Loading @@ -73,6 +75,8 @@ rec { cascadelake = [ "cannonlake" ] ++ inferiors.cannonlake; cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake; tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server; sapphirerapids = [ "tigerlake" ] ++ inferiors.tigerlake; emeraldrapids = [ "sapphirerapids" ] ++ inferiors.sapphirerapids; # CX16 does not exist on alderlake, while it does on nearly all other intel CPUs alderlake = [ ]; Loading pkgs/build-support/cc-wrapper/default.nix +4 −0 Original line number Diff line number Diff line Loading @@ -162,6 +162,8 @@ let tigerlake = versionAtLeast ccVersion "10.0"; knm = versionAtLeast ccVersion "8.0"; alderlake = versionAtLeast ccVersion "12.0"; sapphirerapids = versionAtLeast ccVersion "11.0"; emeraldrapids = versionAtLeast ccVersion "13.0"; # AMD znver1 = true; Loading @@ -181,6 +183,8 @@ let icelake-server = versionAtLeast ccVersion "7.0"; knm = versionAtLeast ccVersion "7.0"; alderlake = versionAtLeast ccVersion "16.0"; sapphirerapids = versionAtLeast ccVersion "12.0"; emeraldrapids = versionAtLeast ccVersion "16.0"; # AMD znver1 = versionAtLeast ccVersion "4.0"; Loading Loading
lib/systems/architectures.nix +4 −0 Original line number Diff line number Diff line Loading @@ -26,6 +26,8 @@ rec { cooperlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; tigerlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; alderlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ]; sapphirerapids = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; emeraldrapids = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; # x86_64 AMD btver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ]; btver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ]; Loading Loading @@ -73,6 +75,8 @@ rec { cascadelake = [ "cannonlake" ] ++ inferiors.cannonlake; cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake; tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server; sapphirerapids = [ "tigerlake" ] ++ inferiors.tigerlake; emeraldrapids = [ "sapphirerapids" ] ++ inferiors.sapphirerapids; # CX16 does not exist on alderlake, while it does on nearly all other intel CPUs alderlake = [ ]; Loading
pkgs/build-support/cc-wrapper/default.nix +4 −0 Original line number Diff line number Diff line Loading @@ -162,6 +162,8 @@ let tigerlake = versionAtLeast ccVersion "10.0"; knm = versionAtLeast ccVersion "8.0"; alderlake = versionAtLeast ccVersion "12.0"; sapphirerapids = versionAtLeast ccVersion "11.0"; emeraldrapids = versionAtLeast ccVersion "13.0"; # AMD znver1 = true; Loading @@ -181,6 +183,8 @@ let icelake-server = versionAtLeast ccVersion "7.0"; knm = versionAtLeast ccVersion "7.0"; alderlake = versionAtLeast ccVersion "16.0"; sapphirerapids = versionAtLeast ccVersion "12.0"; emeraldrapids = versionAtLeast ccVersion "16.0"; # AMD znver1 = versionAtLeast ccVersion "4.0"; Loading