Commit fcf5254f authored by Jay Foad's avatar Jay Foad
Browse files

[AMDGPU] Handle frame index base operands in memOpsHaveSameBasePtr 

Summary:
This is in preparation for getMemOperandsWithOffset returning more base
operands.

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, arphaman, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73454
parent 4332f1a4

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

+0 −5
Original line number Diff line number Diff line
@@ -408,11 +408,6 @@ static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, 
                                  const MachineOperand &BaseOp1,

                                  const MachineInstr &MI2,

                                  const MachineOperand &BaseOp2) {

  // Support only base operands with base registers.

  // Note: this could be extended to support FI operands.

  if (!BaseOp1.isReg() || !BaseOp2.isReg())

    return false;



  if (BaseOp1.isIdenticalTo(BaseOp2))

    return true;