Commit fa43608d authored by 4vtomat's avatar 4vtomat
Browse files

[RISCV][RISCV][clang] Split out SiFive Vector C intrinsics from riscv_vector.td

Since we don't always need the vendor extension to be in riscv_vector.td,
so it's better to make it be in separated header.

Depends on D148223 and D148680

Differential Revision: https://reviews.llvm.org/D148308
parent 8efc7de0
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+1 −0
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@@ -16,6 +16,7 @@
#endif

#include "clang/Basic/riscv_vector_builtins.inc"
#include "clang/Basic/riscv_sifive_vector_builtins.inc"

#undef BUILTIN
#undef TARGET_BUILTIN
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@@ -93,3 +93,12 @@ clang_tablegen(riscv_vector_builtin_cg.inc -gen-riscv-vector-builtin-codegen
clang_tablegen(riscv_vector_builtin_sema.inc -gen-riscv-vector-builtin-sema
  SOURCE riscv_vector.td
  TARGET ClangRISCVVectorBuiltinSema)
clang_tablegen(riscv_sifive_vector_builtins.inc -gen-riscv-sifive-vector-builtins
  SOURCE riscv_sifive_vector.td
  TARGET ClangRISCVSiFiveVectorBuiltins)
clang_tablegen(riscv_sifive_vector_builtin_cg.inc -gen-riscv-sifive-vector-builtin-codegen
  SOURCE riscv_sifive_vector.td
  TARGET ClangRISCVSiFiveVectorBuiltinCG)
clang_tablegen(riscv_sifive_vector_builtin_sema.inc -gen-riscv-sifive-vector-builtin-sema
  SOURCE riscv_sifive_vector.td
  TARGET ClangRISCVSiFiveVectorBuiltinSema)
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@@ -12,6 +12,8 @@
//
//===----------------------------------------------------------------------===//

include "riscv_vector_common.td"

//===----------------------------------------------------------------------===//
// Instruction definitions
//===----------------------------------------------------------------------===//
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@@ -2148,5 +2148,3 @@ let HasMasked = false, HasVL = false, IRName = "" in {
    }
  }
}

include "riscv_sifive_vector.td"
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@@ -22,6 +22,8 @@ class Preprocessor;
namespace sema {
class RISCVIntrinsicManager {
public:
  enum class IntrinsicKind : uint8_t { RVV, SIFIVE_VECTOR };

  virtual ~RISCVIntrinsicManager() = default;

  // Create RISC-V intrinsic and insert into symbol table and return true if
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