Commit f9d7f772 authored by Craig Topper's avatar Craig Topper
Browse files

[RISCV] Have customLegalizeToWOp truncate to the original type instead of i32... 

[RISCV] Have customLegalizeToWOp truncate to the original type instead of i32 now that we use it for i8/i16 as well.

239cfbcc add support for legalizing
i8/i16 UDIV/UREM/SDIV to use *W instructions. So we need to truncate
to i8/i16 if we're legalizing one of those.
parent 1d6df1fc

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+1 −1
Original line number Diff line number Diff line
@@ -1619,7 +1619,7 @@ static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, 
  SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1));

  SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1);

  // ReplaceNodeResults requires we maintain the same type for the return value.

  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes);

  return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes);

}



// Converts the given 32-bit operation to a i64 operation with signed extension

llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

+4 −0
Original line number Diff line number Diff line
@@ -809,6 +809,8 @@ define signext i8 @sext_divw_sext_sext_i8(i8 signext %a, i8 signext %b) nounwind 
; RV64IM-LABEL: sext_divw_sext_sext_i8:

; RV64IM:       # %bb.0:

; RV64IM-NEXT:    divw a0, a0, a1

; RV64IM-NEXT:    slli a0, a0, 56

; RV64IM-NEXT:    srai a0, a0, 56

; RV64IM-NEXT:    ret

  %1 = sdiv i8 %a, %b

  ret i8 %1
@@ -818,6 +820,8 @@ define signext i16 @sext_divw_sext_sext_i16(i16 signext %a, i16 signext %b) noun 
; RV64IM-LABEL: sext_divw_sext_sext_i16:

; RV64IM:       # %bb.0:

; RV64IM-NEXT:    divw a0, a0, a1

; RV64IM-NEXT:    slli a0, a0, 48

; RV64IM-NEXT:    srai a0, a0, 48

; RV64IM-NEXT:    ret

  %1 = sdiv i16 %a, %b

  ret i16 %1