Commit f909ae3f authored by Tom Stellard's avatar Tom Stellard
Browse files

Merging r203581: 

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r203581 | hans | 2014-03-11 11:49:24 -0400 (Tue, 11 Mar 2014) | 7 lines

X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)

This fixes the bug where we would bitcast the 64-bit floating point result
of cmpneqsd to a 64-bit integer even on 32-bit targets.

Differential Revision: http://llvm-reviews.chandlerc.com/D3009

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llvm-svn: 206071
parent 7c40da76

llvm/lib/Target/X86/X86ISelLowering.cpp

+23 −5
Original line number Diff line number Diff line
@@ -17583,12 +17583,30 @@ static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 
          // FIXME: need symbolic constants for these magic numbers.

          // See X86ATTInstPrinter.cpp:printSSECC().

          unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;

          SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,

          SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, CMP00.getValueType(),

                                              CMP00, CMP01,

                                              DAG.getConstant(x86cc, MVT::i8));

          SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,













          MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;

























          if (is64BitFP && !Subtarget->is64Bit()) {













            // On a 32-bit target, we cannot bitcast the 64-bit float to a













            // 64-bit integer, since that's not a legal type. Since













            // OnesOrZeroesF is all ones of all zeroes, we don't need all the













            // bits, but can do this little dance to extract the lowest 32 bits













            // and work with those going forward.













            SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,















                                           OnesOrZeroesF);













          SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,













                                      DAG.getConstant(1, MVT::i32));













            SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,













                                           Vector64);













            OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,













                                        Vector32, DAG.getIntPtrConstant(0));













            IntVT = MVT::i32;













          }

























          SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);













          SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,













                                      DAG.getConstant(1, IntVT));















          SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);















          return OneBitOfTruth;















        }

























llvm/test/CodeGen/X86/isint.ll



+25
−1






























Original line number
Diff line number
Diff line













; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s













; RUN: llc < %s -mtriple=x86_64-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck %s













; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck %s



























; PR19059













; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck -check-prefix=CHECK32 %s































define i32 @isint_return(double %d) nounwind {













; CHECK-LABEL: isint_return:















; CHECK-NOT: xor















; CHECK: cvt















  %i = fptosi double %d to i32









@@ -8,6 +13,24 @@ define i32 @isint_return(double %d) nounwind {













  %e = sitofp i32 %i to double















; CHECK: cmpeqsd















  %c = fcmp oeq double %d, %e













; CHECK32-NOT: movd {{.*}}, %r{{.*}}













; CHECK32-NOT: andq













; CHECK-NEXT: movd













; CHECK-NEXT: andl













  %z = zext i1 %c to i32













  ret i32 %z













}



























define i32 @isint_float_return(float %f) nounwind {













; CHECK-LABEL: isint_float_return:













; CHECK-NOT: xor













; CHECK: cvt













  %i = fptosi float %f to i32













; CHECK-NEXT: cvt













  %g = sitofp i32 %i to float













; CHECK: cmpeqss













  %c = fcmp oeq float %f, %g













; CHECK-NOT: movd {{.*}}, %r{{.*}}















; CHECK-NEXT: movd















; CHECK-NEXT: andl















  %z = zext i1 %c to i32









@@ -17,6 +40,7 @@ define i32 @isint_return(double %d) nounwind {













declare void @foo()































define void @isint_branch(double %d) nounwind {













; CHECK-LABEL: isint_branch:















; CHECK: cvt















  %i = fptosi double %d to i32















; CHECK-NEXT: cvt