Commit f8087884 authored by Jianjian GUAN's avatar Jianjian GUAN
Browse files

[RISCV] Remove experimental for zihintntl

Since zihintntl is ratified now, we could remove the experimental prefix and change its version to 1.0.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D151547
parent 345acac8
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@@ -86,8 +86,8 @@ TARGET_BUILTIN(__builtin_riscv_sm3p0, "UiUi", "nc", "zksh")
TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")

// Zihintntl extension
TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "experimental-zihintntl")
TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "experimental-zihintntl")
TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl")
TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl")

#undef BUILTIN
#undef TARGET_BUILTIN
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// REQUIRES: riscv-registered-target
// RUN: %clang_cc1  -triple riscv32 -target-feature +v -target-feature +experimental-zihintntl -emit-llvm %s -o - \
// RUN: %clang_cc1  -triple riscv32 -target-feature +v -target-feature +zihintntl -emit-llvm %s -o - \
// RUN:     | FileCheck %s

#include <riscv_ntlh.h>
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@@ -143,13 +143,13 @@
// CHECK-C-EXT: __riscv_c 2000000{{$}}
// CHECK-C-EXT: __riscv_compressed 1

// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32izihintntl0p2 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64izihintntl0p2 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
// CHECK-ZIHINTNTL-EXT: __riscv_zihintntl 2000{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu \
// RUN: -march=rv32izihintntl1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL %s
// RUN: %clang -target riscv64-unknown-linux-gnu \
// RUN: -march=rv64izihintntl1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL %s
// CHECK-ZIHINTNTL: __riscv_zihintntl 1000000{{$}}

// RUN: %clang -target riscv32-unknown-linux-gnu \
// RUN: -march=rv32izba1p0 -x c -E -dM %s \
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@@ -120,6 +120,7 @@ on support follow.
     ``Zicntr``       (`See Note <#riscv-i2p1-note>`__)
     ``Zicsr``        (`See Note <#riscv-i2p1-note>`__)
     ``Zifencei``     (`See Note <#riscv-i2p1-note>`__)
     ``Zihintntl``    Supported
     ``Zihintpause``  Assembly Support
     ``Zihpm``        (`See Note <#riscv-i2p1-note>`__)
     ``Zkn``          Supported
@@ -204,9 +205,6 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zicond``
  LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1>`__.

``experimental-zihintntl``
  LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`__.

``experimental-ztso``
  LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25).  The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document.  There are multiple possible mappings, and they are *not* mutually ABI compatible.  The mapping LLVM implements is ABI compatible with the default WMO mapping.  This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status.  User beware.

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@@ -98,6 +98,8 @@ Changes to the PowerPC Backend
Changes to the RISC-V Backend
-----------------------------

* Zihintntl extension version was upgraded to 1.0 and is no longer experimental.

Changes to the WebAssembly Backend
----------------------------------

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