Commit f6111583 authored by Simon Pilgrim's avatar Simon Pilgrim
Browse files

[SelectionDAG] Better ISD::ANY_EXTEND/ISD::ANY_EXTEND_VECTOR_INREG ComputeKnownBits support 

Add DemandedElts handling to ISD::ANY_EXTEND and add missing ISD::ANY_EXTEND_VECTOR_INREG handling. Despite the lack of test changes this code IS being used - its just that the ANY_EXTEND ops are legalized later on (typically to ZERO_EXTEND equivalents) so we typically manage to combine later on.
parent 25afe91f

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

+8 −1
Original line number Diff line number Diff line
@@ -3099,8 +3099,15 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts, 
    Known = Known.sext(BitWidth);

    break;

  }

  case ISD::ANY_EXTEND_VECTOR_INREG: {

    EVT InVT = Op.getOperand(0).getValueType();

    APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements());

    Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1);

    Known = Known.zext(BitWidth, false /* ExtendedBitsAreKnownZero */);

    break;

  }

  case ISD::ANY_EXTEND: {

    Known = computeKnownBits(Op.getOperand(0), Depth+1);

    Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);

    Known = Known.zext(BitWidth, false /* ExtendedBitsAreKnownZero */);

    break;

  }