Commit f4bba07b authored by Mark Murray's avatar Mark Murray
Browse files

[ARM][MVE][Intrinsics] Add MVE VABD intrinsics. Add unit tests. 

Summary: Add MVE VABD intrinsics. Add unit tests.

Reviewers: simon_tatham, ostannard, dmgreen

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D70545
parent 5e6b7287

clang/include/clang/Basic/arm_mve.td

+9 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ foreach n = [ 2, 4 ] in { 
                              "Intrinsic::arm_mve_vld"#n#"q":$IRIntr)>;

}





let params = T.Int in {

def vaddq: Intrinsic<Vector, (args Vector:$a, Vector:$b), (add $a, $b)>;

def vsubq: Intrinsic<Vector, (args Vector:$a, Vector:$b), (sub $a, $b)>;
@@ -41,6 +42,14 @@ def vsubqf: Intrinsic<Vector, (args Vector:$a, Vector:$b), (fsub $a, $b)>, 
}



let params = T.Usual in {

def vabdq: Intrinsic<Vector, (args Vector:$a, Vector:$b),

                             (IRInt<"vabd", [Vector]> $a, $b)>;

}



let params = T.Usual in {

def vabdq_m: Intrinsic<

    Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),

    (IRInt<"abd_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;

def vaddq_m: Intrinsic<

    Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),

    (IRInt<"add_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;

clang/test/CodeGen/arm-mve-intrinsics/vabdq.c

0 → 100644
+95 −0
Original line number Diff line number Diff line 
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py

// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s

// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s



#include <arm_mve.h>



// CHECK-LABEL: @test_vabdq_s8(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])

// CHECK-NEXT:    ret <16 x i8> [[TMP0]]

//

int8x16_t test_vabdq_s8(int8x16_t a, int8x16_t b)

{

#ifdef POLYMORPHIC

    return vabdq(a, b);

#else /* POLYMORPHIC */

    return vabdq_s8(a, b);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vabdq_u32(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])

// CHECK-NEXT:    ret <4 x i32> [[TMP0]]

//

uint32x4_t test_vabdq_u32(uint32x4_t a, uint32x4_t b)

{

#ifdef POLYMORPHIC

    return vabdq(a, b);

#else /* POLYMORPHIC */

    return vabdq_u32(a, b);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vabdq_f32(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]])

// CHECK-NEXT:    ret <8 x half> [[TMP0]]

//

float16x8_t test_vabdq_f32(float16x8_t a, float16x8_t b)

{

#ifdef POLYMORPHIC

    return vabdq(a, b);

#else /* POLYMORPHIC */

    return vabdq_f16(a, b);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vabdq_m_u16(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32

// CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])

// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])

// CHECK-NEXT:    ret <8 x i16> [[TMP2]]

//

uint16x8_t test_vabdq_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)

{

#ifdef POLYMORPHIC

    return vabdq_m(inactive, a, b, p);

#else /* POLYMORPHIC */

    return vabdq_m_u16(inactive, a, b, p);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vabdq_m_s8(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32

// CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])

// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]])

// CHECK-NEXT:    ret <16 x i8> [[TMP2]]

//

int8x16_t test_vabdq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)

{

#ifdef POLYMORPHIC

    return vabdq_m(inactive, a, b, p);

#else /* POLYMORPHIC */

    return vabdq_m_s8(inactive, a, b, p);

#endif /* POLYMORPHIC */

}



// CHECK-LABEL: @test_vabdq_m_f32(

// CHECK-NEXT:  entry:

// CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32

// CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])

// CHECK-NEXT:    [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> [[INACTIVE:%.*]])

// CHECK-NEXT:    ret <4 x float> [[TMP2]]

//

float32x4_t test_vabdq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)

{

#ifdef POLYMORPHIC

    return vabdq_m(inactive, a, b, p);

#else /* POLYMORPHIC */

    return vabdq_m_f32(inactive, a, b, p);

#endif /* POLYMORPHIC */

}

llvm/include/llvm/IR/IntrinsicsARM.td

+6 −0
Original line number Diff line number Diff line
@@ -796,6 +796,9 @@ multiclass IntrinsicSignSuffix<list<LLVMType> rets, list<LLVMType> params = [], 
  def _u: Intrinsic<rets, params, props, name, sdprops>;

}



def int_arm_mve_abd_predicated: Intrinsic<[llvm_anyvector_ty],

   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],

   [IntrNoMem]>;

def int_arm_mve_add_predicated: Intrinsic<[llvm_anyvector_ty],

   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],

   [IntrNoMem]>;
@@ -866,6 +869,9 @@ defm int_arm_mve_sqrshr: ARM_MVE_qrshift<[llvm_i32_ty]>; 
def int_arm_mve_lsll: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty]>;

def int_arm_mve_asrl: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty]>;



def int_arm_mve_vabd: Intrinsic<

   [llvm_anyvector_ty],

   [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;

def int_arm_mve_vadc: Intrinsic<

   [llvm_anyvector_ty, llvm_i32_ty],

   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]>;

llvm/lib/Target/ARM/ARMInstrMVE.td

+53 −9
Original line number Diff line number Diff line
@@ -1664,7 +1664,8 @@ let Predicates = [HasMVEInt] in { 
}





class MVE_VABD_int<string suffix, bit U, bits<2> size, list<dag> pattern=[]>

class MVE_VABD_int<string suffix, bit U, bits<2> size,

                     list<dag> pattern=[]>

  : MVE_int<"vabd", suffix, size, pattern> {



  let Inst{28} = U;
@@ -1676,12 +1677,35 @@ class MVE_VABD_int<string suffix, bit U, bits<2> size, list<dag> pattern=[]> 
  let validForTailPredication = 1;

}



def MVE_VABDs8  : MVE_VABD_int<"s8", 0b0, 0b00>;

def MVE_VABDs16 : MVE_VABD_int<"s16", 0b0, 0b01>;

def MVE_VABDs32 : MVE_VABD_int<"s32", 0b0, 0b10>;

def MVE_VABDu8  : MVE_VABD_int<"u8", 0b1, 0b00>;

def MVE_VABDu16 : MVE_VABD_int<"u16", 0b1, 0b01>;

def MVE_VABDu32 : MVE_VABD_int<"u32", 0b1, 0b10>;

multiclass MVE_VABD_m<MVEVectorVTInfo VTI,

                      Intrinsic unpred_int, Intrinsic pred_int> {

  def "" : MVE_VABD_int<VTI.Suffix, VTI.Unsigned, VTI.Size>;



  let Predicates = [HasMVEInt] in {

    // Unpredicated absolute difference

    def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),

              (VTI.Vec (!cast<Instruction>(NAME)

                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;



    // Predicated absolute difference

    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),

                            (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),

              (VTI.Vec (!cast<Instruction>(NAME)

                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),

                            (i32 1), (VTI.Pred VCCR:$mask),

                            (VTI.Vec MQPR:$inactive)))>;

  }

}



multiclass MVE_VABD<MVEVectorVTInfo VTI>

  : MVE_VABD_m<VTI, int_arm_mve_vabd, int_arm_mve_abd_predicated>;



defm MVE_VABDs8  : MVE_VABD<MVE_v16s8>;

defm MVE_VABDs16 : MVE_VABD<MVE_v8s16>;

defm MVE_VABDs32 : MVE_VABD<MVE_v4s32>;

defm MVE_VABDu8  : MVE_VABD<MVE_v16u8>;

defm MVE_VABDu16 : MVE_VABD<MVE_v8u16>;

defm MVE_VABDu32 : MVE_VABD<MVE_v4u32>;



class MVE_VRHADD<string suffix, bit U, bits<2> size, list<dag> pattern=[]>

  : MVE_int<"vrhadd", suffix, size, pattern> {
@@ -2950,8 +2974,28 @@ class MVE_VABD_fp<string suffix, bit size> 
  let validForTailPredication = 1;

}



def MVE_VABDf32 : MVE_VABD_fp<"f32", 0b0>;

def MVE_VABDf16 : MVE_VABD_fp<"f16", 0b1>;

multiclass MVE_VABDT_fp_m<MVEVectorVTInfo VTI,

                            Intrinsic unpred_int, Intrinsic pred_int> {

  def "" : MVE_VABD_fp<VTI.Suffix, VTI.Size{0}>;



  let Predicates = [HasMVEFloat] in {

    def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),

              (VTI.Vec (!cast<Instruction>(NAME)

                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;

    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),

                            (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),

              (VTI.Vec (!cast<Instruction>(NAME)

                            (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),

                            (i32 1), (VTI.Pred VCCR:$mask),

                            (VTI.Vec MQPR:$inactive)))>;

  }

}



multiclass MVE_VABD_fp_m<MVEVectorVTInfo VTI>

  : MVE_VABDT_fp_m<VTI, int_arm_mve_vabd, int_arm_mve_abd_predicated>;



defm MVE_VABDf32 : MVE_VABD_fp_m<MVE_v4f32>;

defm MVE_VABDf16 : MVE_VABD_fp_m<MVE_v8f16>;



class MVE_VCVT_fix<string suffix, bit fsi, bit U, bit op,

                   Operand imm_operand_type, list<dag> pattern=[]>

llvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll

0 → 100644
+62 −0
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s



define arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> %a, <4 x i32> %b) {

; CHECK-LABEL: test_vabdq_u32:

; CHECK:       @ %bb.0: @ %entry

; CHECK-NEXT:    vabd.s32 q0, q0, q1

; CHECK-NEXT:    bx lr

entry:

  %0 = tail call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>%a, <4 x i32>%b)

  ret <4 x i32> %0

}



declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>)



define arm_aapcs_vfpcc <4 x float> @test_vabdq_f32(<4 x float> %a, <4 x float> %b) {

; CHECK-LABEL: test_vabdq_f32:

; CHECK:       @ %bb.0: @ %entry

; CHECK-NEXT:    vabd.f32 q0, q0, q1

; CHECK-NEXT:    bx lr

entry:

  %0 = tail call <4 x float> @llvm.arm.mve.vabd.v4f32(<4 x float>%a, <4 x float>%b)

  ret <4 x float> %0

}



declare <4 x float> @llvm.arm.mve.vabd.v4f32(<4 x float>, <4 x float>)



define arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {

; CHECK-LABEL: test_vabdq_m_s8:

; CHECK:       @ %bb.0: @ %entry

; CHECK-NEXT:    vmsr p0, r0

; CHECK-NEXT:    vpst

; CHECK-NEXT:    vabdt.s8 q0, q1, q2

; CHECK-NEXT:    bx lr

entry:

  %0 = zext i16 %p to i32

  %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)

  %2 = tail call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)

  ret <16 x i8> %2

}



declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)



declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>)



define arm_aapcs_vfpcc <8 x half> @test_vabdq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) {

; CHECK-LABEL: test_vabdq_m_f16:

; CHECK:       @ %bb.0: @ %entry

; CHECK-NEXT:    vmsr p0, r0

; CHECK-NEXT:    vpst

; CHECK-NEXT:    vabdt.f16 q0, q1, q2

; CHECK-NEXT:    bx lr

entry:

  %0 = zext i16 %p to i32

  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)

  %2 = tail call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> %inactive)

  ret <8 x half> %2

}



declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)



declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>)