Unverified Commit f4231bf4 authored by Pengcheng Wang's avatar Pengcheng Wang Committed by GitHub
Browse files

[RISCV] Replace PostRAScheduler with PostMachineScheduler (#68696) 

Just like what other targets have done.

And this will make DAG mutations like MacroFusion take effect.
parent be215e76

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

+2 −0
Original line number Diff line number Diff line
@@ -248,6 +248,8 @@ class RISCVPassConfig : public TargetPassConfig { 
public:

  RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)

      : TargetPassConfig(TM, PM) {

    if (TM.getOptLevel() != CodeGenOptLevel::None)

      substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);

    setEnableSinkAndFold(EnableSinkFold);

  }

llvm/test/CodeGen/RISCV/O3-pipeline.ll

+1 −1
Original line number Diff line number Diff line
@@ -159,7 +159,7 @@ 
; CHECK-NEXT:       Insert KCFI indirect call checks

; CHECK-NEXT:       MachineDominator Tree Construction

; CHECK-NEXT:       Machine Natural Loop Construction

; CHECK-NEXT:       Post RA top-down list latency scheduler

; CHECK-NEXT:       PostRA Machine Instruction Scheduler

; CHECK-NEXT:       Analyze Machine Code For Garbage Collection

; CHECK-NEXT:       Machine Block Frequency Analysis

; CHECK-NEXT:       MachinePostDominator Tree Construction

llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll

+1 −1
Original line number Diff line number Diff line
@@ -25,8 +25,8 @@ define void @foo(i32 signext %0, i32 signext %1) { 
;

; FUSION-POSTRA-LABEL: foo:

; FUSION-POSTRA:       # %bb.0:

; FUSION-POSTRA-NEXT:    lui a0, %hi(.L.str)

; FUSION-POSTRA-NEXT:    fcvt.s.w fa0, a1

; FUSION-POSTRA-NEXT:    lui a0, %hi(.L.str)

; FUSION-POSTRA-NEXT:    addi a0, a0, %lo(.L.str)

; FUSION-POSTRA-NEXT:    tail bar@plt

  %3 = sitofp i32 %1 to float