Commit f2c87716 authored by Suyog Sarda's avatar Suyog Sarda Committed by Tom Stellard
Browse files

Merging r372480: 

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r372480 | ssarda | 2019-09-21 11:16:37 -0700 (Sat, 21 Sep 2019) | 9 lines

SROA: Check Total Bits of vector type

While Promoting alloca instruction of Vector Type,
Check total size in bits of its slices too.
If they don't match, don't promote the alloca instruction.

Bug : https://bugs.llvm.org/show_bug.cgi?id=42585

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parent e8e0c077

llvm/lib/Transforms/Scalar/SROA.cpp

+8 −0
Original line number Diff line number Diff line
@@ -1888,6 +1888,14 @@ static VectorType *isVectorPromotionViable(Partition &P, const DataLayout &DL) { 
  bool HaveCommonEltTy = true;

  auto CheckCandidateType = [&](Type *Ty) {

    if (auto *VTy = dyn_cast<VectorType>(Ty)) {

      // Return if bitcast to vectors is different for total size in bits.

      if (!CandidateTys.empty()) {

        VectorType *V = CandidateTys[0];

        if (DL.getTypeSizeInBits(VTy) != DL.getTypeSizeInBits(V)) {

          CandidateTys.clear();

          return;

        }

      }

      CandidateTys.push_back(VTy);

      if (!CommonEltTy)

        CommonEltTy = VTy->getElementType();

llvm/test/Transforms/SROA/vector-promotion-different-size.ll

0 → 100644
+24 −0
Original line number Diff line number Diff line 
; RUN: opt < %s -sroa -S | FileCheck %s

target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"



define <4 x i1> @vector_bitcast() {

  ; CHECK-LABEL: @vector_bitcast

  ; CHECK: alloca i1



    %a = alloca <3 x i1>

    store <3 x i1> <i1 1,i1 0,i1 1>, <3 x i1>* %a

    %cast = bitcast <3 x i1>* %a to <4 x i1>*

    %vec = load <4 x i1>, <4 x i1>* %cast

    ret <4 x i1> %vec

}



define void @vector_bitcast_2() {

  ; CHECK-LABEL: @vector_bitcast_2

  ; CHECK: alloca <32 x i16>



    %"sum$1.host2" = alloca <32 x i16>

    store <32 x i16> undef, <32 x i16>* %"sum$1.host2"

    %bc = bitcast <32 x i16>* %"sum$1.host2" to <64 x i16>*

    %bcl = load <64 x i16>, <64 x i16>* %bc

    ret void

}