Commit f0eeb3c7 authored by Quentin Colombet's avatar Quentin Colombet
Browse files

[GISel][CombinerHelper] Combine shuffle_vector scalar to build_vector 

Teach the combiner helper how to replace shuffle_vector of scalars
into build_vector.
I am not particularly happy about having to add this combine, but we
currently get those from <1 x iN> from the IR.

Bonus: This fixes an assert in the shuffle_vector combines since before
this patch, we were expecting vector types.
parent 9baf4958

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

+2 −2
Original line number Diff line number Diff line
@@ -190,7 +190,7 @@ bool CombinerHelper::matchCombineShuffleVector(MachineInstr &MI, 
  Register Src1 = MI.getOperand(1).getReg();

  LLT SrcType = MRI.getType(Src1);

  unsigned DstNumElts = DstType.getNumElements();

  unsigned SrcNumElts = SrcType.getNumElements();

  unsigned SrcNumElts = SrcType.isVector() ? SrcType.getNumElements() : 1;



  // If the resulting vector is smaller than the size of the source

  // vectors being concatenated, we won't be able to replace the
@@ -254,7 +254,7 @@ void CombinerHelper::applyCombineShuffleVector(MachineInstr &MI, 
  Builder.setInsertPt(*MI.getParent(), MI);

  Register NewDstReg = MRI.cloneVirtualRegister(DstReg);



  Builder.buildConcatVectors(NewDstReg, Ops);

  Builder.buildMerge(NewDstReg, Ops);



  MI.eraseFromParent();

  replaceRegWith(MRI, DstReg, NewDstReg);

llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir

+63 −0
Original line number Diff line number Diff line
@@ -351,3 +351,66 @@ body: | 
    %6:_(<4 x p0>) = G_SHUFFLE_VECTOR %4(<2 x p0>), %5(<2 x p0>), shufflemask(0,1,2,3)

    RET_ReallyLR implicit %6

...



# Check that shuffle_vector on scalars gets combined into build_vector.

---

name: shuffle_vector_on_scalars_to_build_vector_ptr

tracksRegLiveness: true

body:             |

  bb.1:

    liveins: $x0, $x1



    ; CHECK-LABEL: name: shuffle_vector_on_scalars_to_build_vector_ptr

    ; CHECK: liveins: $x0, $x1

    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0

    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1

    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x p0>) = G_BUILD_VECTOR [[COPY]](p0), [[COPY1]](p0), [[COPY]](p0), [[COPY1]](p0)

    ; CHECK: RET_ReallyLR implicit [[BUILD_VECTOR]](<4 x p0>)

    %0:_(p0) = COPY $x0

    %1:_(p0) = COPY $x1

    %6:_(<4 x p0>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0,1,0,1)

    RET_ReallyLR implicit %6

...



# Check that shuffle_vector on scalars gets combined into build_vector,

# even if we swap the order of the operands.

---

name: shuffle_vector_on_scalars_to_build_vector_swap_ptr

tracksRegLiveness: true

body:             |

  bb.1:

    liveins: $x0, $x1



    ; CHECK-LABEL: name: shuffle_vector_on_scalars_to_build_vector_swap_ptr

    ; CHECK: liveins: $x0, $x1

    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0

    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1

    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY1]](p0), [[COPY]](p0)

    ; CHECK: RET_ReallyLR implicit [[BUILD_VECTOR]](<2 x p0>)

    %0:_(p0) = COPY $x0

    %1:_(p0) = COPY $x1

    %6:_(<2 x p0>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(1,0)

    RET_ReallyLR implicit %6

...



# Check that we properly use undef values when shuffle_vector

# on scalars gets lowered to build_vector.

---

name: shuffle_vector_on_scalars_to_build_vector_with_undef

tracksRegLiveness: true

body:             |

  bb.1:

    liveins: $x0, $x1



    ; CHECK-LABEL: name: shuffle_vector_on_scalars_to_build_vector_with_undef

    ; CHECK: liveins: $x0, $x1

    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0

    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1

    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF

    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[DEF]](s64), [[DEF]](s64), [[COPY1]](s64)

    ; CHECK: RET_ReallyLR implicit [[BUILD_VECTOR]](<4 x s64>)

    %0:_(s64) = COPY $x0

    %1:_(s64) = COPY $x1

    %6:_(<4 x s64>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0,-1,-1,1)

    RET_ReallyLR implicit %6

...