Commit f01b9aa8 authored by David Green's avatar David Green
Browse files

[MachineScheduler] Enable AA in PostRA Machine scheduler 

This adds AA to Post-RA Machine Scheduling, allowing the pass more
freedom when handling memory operations.

My understanding is that this was just never done, not that it is
inherently incorrect to do so. The older PostRA List scheduler already
makes use of AA, it's just that the MI PostRA Scheduler was never taught
to use it.

Differential Revision: https://reviews.llvm.org/D69814
parent 2d21068d

llvm/lib/CodeGen/MachineScheduler.cpp

+2 −0
Original line number Diff line number Diff line
@@ -238,6 +238,7 @@ void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { 
  AU.setPreservesCFG();

  AU.addRequired<MachineDominatorTree>();

  AU.addRequired<MachineLoopInfo>();

  AU.addRequired<AAResultsWrapperPass>();

  AU.addRequired<TargetPassConfig>();

  MachineFunctionPass::getAnalysisUsage(AU);

}
@@ -412,6 +413,7 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) { 
  MF = &mf;

  MLI = &getAnalysis<MachineLoopInfo>();

  PassConfig = &getAnalysis<TargetPassConfig>();

  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();



  if (VerifyScheduling)

    MF->verify(this, "Before post machine scheduling.");

llvm/test/CodeGen/AArch64/merge-store-dependency.ll

+3 −3
Original line number Diff line number Diff line
@@ -17,15 +17,15 @@ define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg 
; A53-NEXT:    movi v0.2d, #0000000000000000

; A53-NEXT:    mov x8, x0

; A53-NEXT:    mov x19, x8

; A53-NEXT:    mov w9, #256

; A53-NEXT:    mov w0, w1

; A53-NEXT:    str q0, [x8]

; A53-NEXT:    mov w9, #256

; A53-NEXT:    str q0, [x19, #16]!

; A53-NEXT:    strh w9, [x8, #24]

; A53-NEXT:    str w1, [x19]

; A53-NEXT:    mov w1, #4

; A53-NEXT:    stp x2, x3, [x8, #32]

; A53-NEXT:    mov x2, x8

; A53-NEXT:    str q0, [x8]

; A53-NEXT:    strh w9, [x8, #24]

; A53-NEXT:    str wzr, [x8, #20]

; A53-NEXT:    bl fcntl

; A53-NEXT:    adrp x9, gv0

llvm/test/CodeGen/PowerPC/extract-and-store.ll

+12 −12
Original line number Diff line number Diff line
@@ -484,8 +484,8 @@ define dso_local void @test_consecutive_i32(<4 x i32> %a, i32* nocapture %b) loc 
; CHECK:       # %bb.0: # %entry

; CHECK-NEXT:    xxsldwi vs0, vs34, vs34, 2

; CHECK-NEXT:    li r3, 4

; CHECK-NEXT:    stfiwx f0, 0, r5

; CHECK-NEXT:    stxsiwx vs34, r5, r3

; CHECK-NEXT:    stfiwx f0, 0, r5

; CHECK-NEXT:    blr

;

; CHECK-BE-LABEL: test_consecutive_i32:
@@ -501,8 +501,8 @@ define dso_local void @test_consecutive_i32(<4 x i32> %a, i32* nocapture %b) loc 
; CHECK-P9:       # %bb.0: # %entry

; CHECK-P9-NEXT:    xxsldwi vs0, vs34, vs34, 2

; CHECK-P9-NEXT:    li r3, 4

; CHECK-P9-NEXT:    stfiwx f0, 0, r5

; CHECK-P9-NEXT:    stxsiwx vs34, r5, r3

; CHECK-P9-NEXT:    stfiwx f0, 0, r5

; CHECK-P9-NEXT:    blr

;

; CHECK-P9-BE-LABEL: test_consecutive_i32:
@@ -590,8 +590,8 @@ define dso_local void @test_stores_exceed_vec_size(<4 x i32> %a, i32* nocapture 
; CHECK-BE-NEXT:    li r4, 20

; CHECK-BE-NEXT:    stxsiwx vs34, r5, r3

; CHECK-BE-NEXT:    xxsldwi vs0, vs34, vs0, 2

; CHECK-BE-NEXT:    stxvw4x vs0, 0, r5

; CHECK-BE-NEXT:    stfiwx f1, r5, r4

; CHECK-BE-NEXT:    stxvw4x vs0, 0, r5

; CHECK-BE-NEXT:    blr

;

; CHECK-P9-LABEL: test_stores_exceed_vec_size:
@@ -599,13 +599,13 @@ define dso_local void @test_stores_exceed_vec_size(<4 x i32> %a, i32* nocapture 
; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_0@toc@ha

; CHECK-P9-NEXT:    addi r3, r3, .LCPI16_0@toc@l

; CHECK-P9-NEXT:    lxvx vs35, 0, r3

; CHECK-P9-NEXT:    li r3, 16

; CHECK-P9-NEXT:    vperm v3, v2, v2, v3

; CHECK-P9-NEXT:    xxsldwi vs0, vs34, vs34, 1

; CHECK-P9-NEXT:    stxv vs35, 0(r5)

; CHECK-P9-NEXT:    li r3, 16

; CHECK-P9-NEXT:    stfiwx f0, r5, r3

; CHECK-P9-NEXT:    li r3, 20

; CHECK-P9-NEXT:    stxsiwx vs34, r5, r3

; CHECK-P9-NEXT:    vperm v3, v2, v2, v3

; CHECK-P9-NEXT:    stxv vs35, 0(r5)

; CHECK-P9-NEXT:    blr

;

; CHECK-P9-BE-LABEL: test_stores_exceed_vec_size:
@@ -613,10 +613,10 @@ define dso_local void @test_stores_exceed_vec_size(<4 x i32> %a, i32* nocapture 
; CHECK-P9-BE-NEXT:    xxspltw vs0, vs34, 0

; CHECK-P9-BE-NEXT:    xxsldwi vs0, vs34, vs0, 2

; CHECK-P9-BE-NEXT:    li r3, 16

; CHECK-P9-BE-NEXT:    stxv vs0, 0(r5)

; CHECK-P9-BE-NEXT:    xxsldwi vs0, vs34, vs34, 1

; CHECK-P9-BE-NEXT:    stxsiwx vs34, r5, r3

; CHECK-P9-BE-NEXT:    li r3, 20

; CHECK-P9-BE-NEXT:    stxv vs0, 0(r5)

; CHECK-P9-BE-NEXT:    xxsldwi vs0, vs34, vs34, 1

; CHECK-P9-BE-NEXT:    stfiwx f0, r5, r3

; CHECK-P9-BE-NEXT:    blr

entry:
@@ -930,8 +930,8 @@ define void @test_elements_from_two_vec(<4 x i32> %a, <4 x i32> %b, i32* nocaptu 
; CHECK-BE:       # %bb.0: # %entry

; CHECK-BE-NEXT:    xxsldwi vs0, vs34, vs34, 3

; CHECK-BE-NEXT:    li r3, 4

; CHECK-BE-NEXT:    stfiwx f0, r7, r3

; CHECK-BE-NEXT:    stxsiwx vs35, 0, r7

; CHECK-BE-NEXT:    stfiwx f0, r7, r3

; CHECK-BE-NEXT:    blr

;

; CHECK-P9-LABEL: test_elements_from_two_vec:
@@ -977,19 +977,19 @@ define dso_local void @test_elements_from_three_vec(<4 x float> %a, <4 x float> 
; CHECK-BE-NEXT:    xxsldwi vs1, vs35, vs35, 1

; CHECK-BE-NEXT:    li r3, 4

; CHECK-BE-NEXT:    li r4, 8

; CHECK-BE-NEXT:    stxsiwx vs36, r9, r4

; CHECK-BE-NEXT:    stfiwx f1, r9, r3

; CHECK-BE-NEXT:    stfiwx f0, 0, r9

; CHECK-BE-NEXT:    stxsiwx vs36, r9, r4

; CHECK-BE-NEXT:    blr

;

; CHECK-P9-LABEL: test_elements_from_three_vec:

; CHECK-P9:       # %bb.0: # %entry

; CHECK-P9-NEXT:    xxsldwi vs0, vs34, vs34, 3

; CHECK-P9-NEXT:    li r3, 4

; CHECK-P9-NEXT:    stfiwx f0, 0, r9

; CHECK-P9-NEXT:    xxsldwi vs0, vs36, vs36, 1

; CHECK-P9-NEXT:    stxsiwx vs35, r9, r3

; CHECK-P9-NEXT:    li r3, 8

; CHECK-P9-NEXT:    stfiwx f0, 0, r9

; CHECK-P9-NEXT:    xxsldwi vs0, vs36, vs36, 1

; CHECK-P9-NEXT:    stfiwx f0, r9, r3

; CHECK-P9-NEXT:    blr

;

llvm/test/CodeGen/PowerPC/f128-aggregates.ll

+2 −2
Original line number Diff line number Diff line
@@ -353,10 +353,10 @@ define fp128 @sum_float128(i32 signext %count, ...) { 
; CHECK-NEXT:    addi r3, r1, 40

; CHECK-NEXT:    lxvx v3, 0, r3

; CHECK-NEXT:    xsaddqp v2, v3, v2

; CHECK-NEXT:    addi [[REG2:r[0-9]+]], r1, 72

; CHECK-NEXT:    std [[REG2]], -8(r1)

; CHECK-NEXT:    lxv v3, 16(r3)

; CHECK-NEXT:    xsaddqp v2, v2, v3

; CHECK-NEXT:    addi [[REG2:r[0-9]+]], r1, 72

; CHECK-NEXT:    std [[REG2]], -8(r1)

; CHECK-NEXT:    blr

entry:

  %ap = alloca i8*, align 8

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll

+16 −16
Original line number Diff line number Diff line
@@ -328,27 +328,27 @@ define void @test16elt(<16 x i64>* noalias nocapture sret %agg.result, <16 x flo 
; CHECK-P9-NEXT:    lxv vs2, 48(r4)

; CHECK-P9-NEXT:    xxswapd vs8, vs2

; CHECK-P9-NEXT:    xscvspdpn f8, vs8

; CHECK-P9-NEXT:    xvcvdpuxds vs0, vs0

; CHECK-P9-NEXT:    stxv vs5, 32(r3)

; CHECK-P9-NEXT:    xvcvdpuxds vs6, vs6

; CHECK-P9-NEXT:    xvcvdpuxds vs4, vs4

; CHECK-P9-NEXT:    xscvspdpn f3, vs3

; CHECK-P9-NEXT:    xxmrghd vs3, vs7, vs3

; CHECK-P9-NEXT:    xxsldwi vs7, vs2, vs2, 3

; CHECK-P9-NEXT:    xvcvdpuxds vs0, vs0

; CHECK-P9-NEXT:    xvcvdpuxds vs6, vs6

; CHECK-P9-NEXT:    stxv vs6, 64(r3)

; CHECK-P9-NEXT:    xscvspdpn f7, vs7

; CHECK-P9-NEXT:    xxmrghd vs7, vs8, vs7

; CHECK-P9-NEXT:    xscvspdpn f8, vs2

; CHECK-P9-NEXT:    xxsldwi vs2, vs2, vs2, 1

; CHECK-P9-NEXT:    stxv vs6, 64(r3)

; CHECK-P9-NEXT:    xvcvdpuxds vs4, vs4

; CHECK-P9-NEXT:    xscvspdpn f2, vs2

; CHECK-P9-NEXT:    xxmrghd vs2, vs8, vs2

; CHECK-P9-NEXT:    xvcvdpuxds vs3, vs3

; CHECK-P9-NEXT:    xvcvdpuxds vs7, vs7

; CHECK-P9-NEXT:    xscvspdpn f2, vs2

; CHECK-P9-NEXT:    stxv vs3, 80(r3)

; CHECK-P9-NEXT:    xxmrghd vs2, vs8, vs2

; CHECK-P9-NEXT:    xvcvdpuxds vs2, vs2

; CHECK-P9-NEXT:    stxv vs2, 112(r3)

; CHECK-P9-NEXT:    stxv vs7, 96(r3)

; CHECK-P9-NEXT:    stxv vs2, 112(r3)

; CHECK-P9-NEXT:    stxv vs4, 48(r3)

; CHECK-P9-NEXT:    stxv vs5, 32(r3)

; CHECK-P9-NEXT:    stxv vs0, 16(r3)

; CHECK-P9-NEXT:    stxv vs1, 0(r3)

; CHECK-P9-NEXT:    blr
@@ -738,27 +738,27 @@ define void @test16elt_signed(<16 x i64>* noalias nocapture sret %agg.result, <1 
; CHECK-P9-NEXT:    lxv vs2, 48(r4)

; CHECK-P9-NEXT:    xxswapd vs8, vs2

; CHECK-P9-NEXT:    xscvspdpn f8, vs8

; CHECK-P9-NEXT:    xvcvdpuxds vs0, vs0

; CHECK-P9-NEXT:    stxv vs5, 32(r3)

; CHECK-P9-NEXT:    xvcvdpuxds vs6, vs6

; CHECK-P9-NEXT:    xvcvdpuxds vs4, vs4

; CHECK-P9-NEXT:    xscvspdpn f3, vs3

; CHECK-P9-NEXT:    xxmrghd vs3, vs7, vs3

; CHECK-P9-NEXT:    xxsldwi vs7, vs2, vs2, 3

; CHECK-P9-NEXT:    xvcvdpuxds vs0, vs0

; CHECK-P9-NEXT:    xvcvdpuxds vs6, vs6

; CHECK-P9-NEXT:    stxv vs6, 64(r3)

; CHECK-P9-NEXT:    xscvspdpn f7, vs7

; CHECK-P9-NEXT:    xxmrghd vs7, vs8, vs7

; CHECK-P9-NEXT:    xscvspdpn f8, vs2

; CHECK-P9-NEXT:    xxsldwi vs2, vs2, vs2, 1

; CHECK-P9-NEXT:    stxv vs6, 64(r3)

; CHECK-P9-NEXT:    xvcvdpuxds vs4, vs4

; CHECK-P9-NEXT:    xscvspdpn f2, vs2

; CHECK-P9-NEXT:    xxmrghd vs2, vs8, vs2

; CHECK-P9-NEXT:    xvcvdpuxds vs3, vs3

; CHECK-P9-NEXT:    xvcvdpuxds vs7, vs7

; CHECK-P9-NEXT:    xscvspdpn f2, vs2

; CHECK-P9-NEXT:    stxv vs3, 80(r3)

; CHECK-P9-NEXT:    xxmrghd vs2, vs8, vs2

; CHECK-P9-NEXT:    xvcvdpuxds vs2, vs2

; CHECK-P9-NEXT:    stxv vs2, 112(r3)

; CHECK-P9-NEXT:    stxv vs7, 96(r3)

; CHECK-P9-NEXT:    stxv vs2, 112(r3)

; CHECK-P9-NEXT:    stxv vs4, 48(r3)

; CHECK-P9-NEXT:    stxv vs5, 32(r3)

; CHECK-P9-NEXT:    stxv vs0, 16(r3)

; CHECK-P9-NEXT:    stxv vs1, 0(r3)

; CHECK-P9-NEXT:    blr