Commit edce93c9 authored by Simon Pilgrim's avatar Simon Pilgrim
Browse files

[X86] Lower abdu(lhs, rhs) -> or(usubsat(lhs,rhs), usubsat(rhs,lhs)) 

Adds pre-SSE4 v8i16 abdu handling - we already have something similar for umax(x,y) -> add(x,usubsat(y,x)) / umin(x,y) -> sub(x,usubsat(x,y))

(I'm starting to look at adding generic TargetLowering expandABD() handling and came across this missed opportunity).

Inspiration: http://0x80.pl/notesen/2018-03-11-sse-abs-unsigned.html

Alive2: https://alive2.llvm.org/ce/z/gMhaTa
parent 419bc856

llvm/lib/Target/X86/X86ISelLowering.cpp

+7 −0
Original line number Diff line number Diff line
@@ -1079,6 +1079,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, 
    }















    setOperationAction(ISD::ABDU,               MVT::v16i8, Custom);













    setOperationAction(ISD::ABDU,               MVT::v8i16, Custom);















    setOperationAction(ISD::ABDS,               MVT::v8i16, Custom);





























    setOperationAction(ISD::UADDSAT,            MVT::v16i8, Legal);










@@ -30244,6 +30245,12 @@ static SDValue LowerABD(SDValue Op, const X86Subtarget &Subtarget,













    return DAG.getNode(ISD::SUB, dl, VT, Max, Min);















  }



























  // abdu(lhs, rhs) -> or(usubsat(lhs,rhs), usubsat(rhs,lhs))













  if (!IsSigned && TLI.isOperationLegal(ISD::USUBSAT, VT))













    return DAG.getNode(ISD::OR, dl, VT,













                       DAG.getNode(ISD::USUBSAT, dl, VT, LHS, RHS),













                       DAG.getNode(ISD::USUBSAT, dl, VT, RHS, LHS));



























  // abds(lhs, rhs) -> select(sgt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))















  // abdu(lhs, rhs) -> select(ugt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))















  EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);

























llvm/test/CodeGen/X86/abdu-vector-128.ll



+21
−129






























Original line number
Diff line number
Diff line








@@ -58,56 +58,10 @@ define <16 x i8> @abd_ext_v16i8_undef(<16 x i8> %a, <16 x i8> %b) nounwind {













define <8 x i16> @abd_ext_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {















; SSE2-LABEL: abd_ext_v8i16:















; SSE2:       # %bb.0:













; SSE2-NEXT:    pxor %xmm5, %xmm5













; SSE2-NEXT:    movdqa %xmm0, %xmm2













; SSE2-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm5[4],xmm2[5],xmm5[5],xmm2[6],xmm5[6],xmm2[7],xmm5[7]













; SSE2-NEXT:    movdqa %xmm2, %xmm3













; SSE2-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1]













; SSE2-NEXT:    punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm5[2],xmm2[3],xmm5[3]













; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3]













; SSE2-NEXT:    movdqa %xmm0, %xmm4













; SSE2-NEXT:    punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]













; SSE2-NEXT:    punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm5[2],xmm0[3],xmm5[3]













; SSE2-NEXT:    movdqa %xmm1, %xmm6













; SSE2-NEXT:    punpckhwd {{.*#+}} xmm6 = xmm6[4],xmm5[4],xmm6[5],xmm5[5],xmm6[6],xmm5[6],xmm6[7],xmm5[7]













; SSE2-NEXT:    movdqa %xmm6, %xmm7













; SSE2-NEXT:    punpckldq {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]













; SSE2-NEXT:    psubq %xmm7, %xmm3













; SSE2-NEXT:    punpckhdq {{.*#+}} xmm6 = xmm6[2],xmm5[2],xmm6[3],xmm5[3]













; SSE2-NEXT:    psubq %xmm6, %xmm2













; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1],xmm1[2],xmm5[2],xmm1[3],xmm5[3]













; SSE2-NEXT:    movdqa %xmm1, %xmm6













; SSE2-NEXT:    punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]













; SSE2-NEXT:    psubq %xmm6, %xmm4













; SSE2-NEXT:    punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm5[2],xmm1[3],xmm5[3]













; SSE2-NEXT:    psubq %xmm1, %xmm0













; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm3[1,1,3,3]













; SSE2-NEXT:    psrad $31, %xmm1













; SSE2-NEXT:    pxor %xmm1, %xmm3













; SSE2-NEXT:    psubq %xmm1, %xmm3













; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]













; SSE2-NEXT:    psrad $31, %xmm1













; SSE2-NEXT:    pxor %xmm1, %xmm2













; SSE2-NEXT:    psubq %xmm1, %xmm2













; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm4[1,1,3,3]













; SSE2-NEXT:    psrad $31, %xmm1













; SSE2-NEXT:    pxor %xmm1, %xmm4













; SSE2-NEXT:    psubq %xmm1, %xmm4













; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]













; SSE2-NEXT:    psrad $31, %xmm1













; SSE2-NEXT:    pxor %xmm1, %xmm0













; SSE2-NEXT:    psubq %xmm1, %xmm0













; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]













; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]













; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm4[0,2,2,3]













; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]













; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]













; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]













; SSE2-NEXT:    pshuflw {{.*#+}} xmm2 = xmm0[0,1,0,2,4,5,6,7]













; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]













; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]













; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]













; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]













; SSE2-NEXT:    movdqa %xmm1, %xmm2













; SSE2-NEXT:    psubusw %xmm0, %xmm2













; SSE2-NEXT:    psubusw %xmm1, %xmm0













; SSE2-NEXT:    por %xmm2, %xmm0















; SSE2-NEXT:    retq















;















; SSE42-LABEL: abd_ext_v8i16:










@@ -135,56 +89,10 @@ define <8 x i16> @abd_ext_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {













define <8 x i16> @abd_ext_v8i16_undef(<8 x i16> %a, <8 x i16> %b) nounwind {















; SSE2-LABEL: abd_ext_v8i16_undef:















; SSE2:       # %bb.0:













; SSE2-NEXT:    pxor %xmm5, %xmm5













; SSE2-NEXT:    movdqa %xmm0, %xmm2













; SSE2-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm5[4],xmm2[5],xmm5[5],xmm2[6],xmm5[6],xmm2[7],xmm5[7]













; SSE2-NEXT:    movdqa %xmm2, %xmm3













; SSE2-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1]













; SSE2-NEXT:    punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm5[2],xmm2[3],xmm5[3]













; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3]













; SSE2-NEXT:    movdqa %xmm0, %xmm4













; SSE2-NEXT:    punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]













; SSE2-NEXT:    punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm5[2],xmm0[3],xmm5[3]













; SSE2-NEXT:    movdqa %xmm1, %xmm6













; SSE2-NEXT:    punpckhwd {{.*#+}} xmm6 = xmm6[4],xmm5[4],xmm6[5],xmm5[5],xmm6[6],xmm5[6],xmm6[7],xmm5[7]













; SSE2-NEXT:    movdqa %xmm6, %xmm7













; SSE2-NEXT:    punpckldq {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]













; SSE2-NEXT:    psubq %xmm7, %xmm3













; SSE2-NEXT:    punpckhdq {{.*#+}} xmm6 = xmm6[2],xmm5[2],xmm6[3],xmm5[3]













; SSE2-NEXT:    psubq %xmm6, %xmm2













; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1],xmm1[2],xmm5[2],xmm1[3],xmm5[3]













; SSE2-NEXT:    movdqa %xmm1, %xmm6













; SSE2-NEXT:    punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]













; SSE2-NEXT:    psubq %xmm6, %xmm4













; SSE2-NEXT:    punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm5[2],xmm1[3],xmm5[3]













; SSE2-NEXT:    psubq %xmm1, %xmm0













; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm3[1,1,3,3]













; SSE2-NEXT:    psrad $31, %xmm1













; SSE2-NEXT:    pxor %xmm1, %xmm3













; SSE2-NEXT:    psubq %xmm1, %xmm3













; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]













; SSE2-NEXT:    psrad $31, %xmm1













; SSE2-NEXT:    pxor %xmm1, %xmm2













; SSE2-NEXT:    psubq %xmm1, %xmm2













; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm4[1,1,3,3]













; SSE2-NEXT:    psrad $31, %xmm1













; SSE2-NEXT:    pxor %xmm1, %xmm4













; SSE2-NEXT:    psubq %xmm1, %xmm4













; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]













; SSE2-NEXT:    psrad $31, %xmm1













; SSE2-NEXT:    pxor %xmm1, %xmm0













; SSE2-NEXT:    psubq %xmm1, %xmm0













; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]













; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]













; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm4[0,2,2,3]













; SSE2-NEXT:    pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]













; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]













; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]













; SSE2-NEXT:    pshuflw {{.*#+}} xmm2 = xmm0[0,1,0,2,4,5,6,7]













; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]













; SSE2-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]













; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]













; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]













; SSE2-NEXT:    movdqa %xmm1, %xmm2













; SSE2-NEXT:    psubusw %xmm0, %xmm2













; SSE2-NEXT:    psubusw %xmm1, %xmm0













; SSE2-NEXT:    por %xmm2, %xmm0















; SSE2-NEXT:    retq















;















; SSE42-LABEL: abd_ext_v8i16_undef:










@@ -481,13 +389,10 @@ define <16 x i8> @abd_minmax_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {













define <8 x i16> @abd_minmax_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {















; SSE2-LABEL: abd_minmax_v8i16:















; SSE2:       # %bb.0:













; SSE2-NEXT:    movdqa %xmm0, %xmm2













; SSE2-NEXT:    psubusw %xmm1, %xmm2













; SSE2-NEXT:    psubusw %xmm0, %xmm1













; SSE2-NEXT:    paddw %xmm0, %xmm1













; SSE2-NEXT:    psubw %xmm0, %xmm2













; SSE2-NEXT:    paddw %xmm1, %xmm2













; SSE2-NEXT:    movdqa %xmm2, %xmm0













; SSE2-NEXT:    movdqa %xmm1, %xmm2













; SSE2-NEXT:    psubusw %xmm0, %xmm2













; SSE2-NEXT:    psubusw %xmm1, %xmm0













; SSE2-NEXT:    por %xmm2, %xmm0















; SSE2-NEXT:    retq















;















; SSE42-LABEL: abd_minmax_v8i16:










@@ -653,17 +558,10 @@ define <16 x i8> @abd_cmp_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {













define <8 x i16> @abd_cmp_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {















; SSE2-LABEL: abd_cmp_v8i16:















; SSE2:       # %bb.0:













; SSE2-NEXT:    movdqa %xmm1, %xmm3













; SSE2-NEXT:    psubusw %xmm0, %xmm3













; SSE2-NEXT:    pxor %xmm2, %xmm2













; SSE2-NEXT:    pcmpeqw %xmm3, %xmm2













; SSE2-NEXT:    movdqa %xmm0, %xmm3













; SSE2-NEXT:    psubw %xmm1, %xmm3













; SSE2-NEXT:    psubw %xmm0, %xmm1













; SSE2-NEXT:    pand %xmm2, %xmm3













; SSE2-NEXT:    pandn %xmm1, %xmm2













; SSE2-NEXT:    por %xmm3, %xmm2













; SSE2-NEXT:    movdqa %xmm2, %xmm0













; SSE2-NEXT:    movdqa %xmm1, %xmm2













; SSE2-NEXT:    psubusw %xmm0, %xmm2













; SSE2-NEXT:    psubusw %xmm1, %xmm0













; SSE2-NEXT:    por %xmm2, %xmm0















; SSE2-NEXT:    retq















;















; SSE42-LABEL: abd_cmp_v8i16:










@@ -890,19 +788,13 @@ define <2 x i64> @abd_cmp_v2i64_multiuse_cmp(<2 x i64> %a, <2 x i64> %b) nounwin













define <8 x i16> @abd_cmp_v8i16_multiuse_sub(<8 x i16> %a, <8 x i16> %b) nounwind {















; SSE2-LABEL: abd_cmp_v8i16_multiuse_sub:















; SSE2:       # %bb.0:













; SSE2-NEXT:    movdqa %xmm0, %xmm2













; SSE2-NEXT:    psubw %xmm1, %xmm2















; SSE2-NEXT:    movdqa %xmm1, %xmm3















; SSE2-NEXT:    psubusw %xmm0, %xmm3













; SSE2-NEXT:    pxor %xmm2, %xmm2













; SSE2-NEXT:    pcmpeqw %xmm3, %xmm2













; SSE2-NEXT:    movdqa %xmm0, %xmm3













; SSE2-NEXT:    psubw %xmm1, %xmm3













; SSE2-NEXT:    psubw %xmm0, %xmm1













; SSE2-NEXT:    movdqa %xmm3, %xmm0













; SSE2-NEXT:    pand %xmm2, %xmm0













; SSE2-NEXT:    pandn %xmm1, %xmm2













; SSE2-NEXT:    por %xmm0, %xmm2













; SSE2-NEXT:    paddw %xmm3, %xmm2













; SSE2-NEXT:    movdqa %xmm2, %xmm0













; SSE2-NEXT:    psubusw %xmm1, %xmm0













; SSE2-NEXT:    por %xmm3, %xmm0













; SSE2-NEXT:    paddw %xmm2, %xmm0















; SSE2-NEXT:    retq















;















; SSE42-LABEL: abd_cmp_v8i16_multiuse_sub:

































llvm/test/CodeGen/X86/midpoint-int-vec-128.ll



+1
−3






























Original line number
Diff line number
Diff line








@@ -1922,9 +1922,7 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun













; SSE2-NEXT:    movdqa %xmm0, %xmm3















; SSE2-NEXT:    psubusw %xmm1, %xmm3















; SSE2-NEXT:    psubusw %xmm0, %xmm1













; SSE2-NEXT:    paddw %xmm0, %xmm1













; SSE2-NEXT:    psubw %xmm0, %xmm3













; SSE2-NEXT:    paddw %xmm1, %xmm3













; SSE2-NEXT:    por %xmm1, %xmm3















; SSE2-NEXT:    psrlw $1, %xmm3















; SSE2-NEXT:    pmullw %xmm2, %xmm3















; SSE2-NEXT:    paddw %xmm3, %xmm0