Commit ecc99079 authored by Simon Dardis's avatar Simon Dardis
Browse files

Merging r325653 with test fixups: 

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r325653 | sdardis | 2018-02-21 00:06:53 +0000 (Wed, 21 Feb 2018) | 31 lines

[mips] Spectre variant two mitigation for MIPSR2

This patch provides mitigation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It implements the LLVM part of
-mindirect-jump=hazard. It is _not_ enabled by default for the P5600.

The migitation strategy suggested by MIPS for these processors is to use
hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.

These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.

These instructions are used with the attribute +use-indirect-jump-hazard
when branching indirectly and for indirect function calls.

These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.

Performance benchmarking of this option with -fpic and lld using
-z hazardplt shows a difference of overall 10%~ time increase
for the LLVM testsuite. Certain benchmarks such as methcall show a
substantially larger increase in time due to their nature.

Reviewers: atanasyan, zoran.jovanovic

Differential Revision: https://reviews.llvm.org/D43486

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llvm-svn: 329798
parent 6ce72f28

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

+1 −0
Original line number Diff line number Diff line
@@ -5136,6 +5136,7 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 
  // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction

  // and registers Rd and Base for microMIPS lwp instruction

  case Mips::JALR_HB:

  case Mips::JALR_HB64:

  case Mips::JALRC_HB_MMR6:

  case Mips::JALRC_MMR6:

    if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())

llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

+6 −0
Original line number Diff line number Diff line
@@ -1886,6 +1886,12 @@ let AddedComplexity = 41 in { 


def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;



def TAILCALLREG_MMR6  : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;



def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,

                                                         GPR32Opnd>,

                                ISA_MICROMIPS32R6;



def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),

              (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;

llvm/lib/Target/Mips/MicroMipsInstrInfo.td

+6 −0
Original line number Diff line number Diff line
@@ -1003,6 +1003,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { 


def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>, ISA_MIPS1_NOT_32R6_64R6;



def TAILCALLREG_MM  : TailCallReg<JRC16_MM, GPR32Opnd>,

                      ISA_MICROMIPS32_NOT_MIPS32R6;



def PseudoIndirectBranch_MM : PseudoIndirectBranchBase<JR_MM, GPR32Opnd>,

                              ISA_MICROMIPS32_NOT_MIPS32R6;



let DecoderNamespace = "MicroMips" in {

  def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,

                 RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;

llvm/lib/Target/Mips/Mips.td

+4 −0
Original line number Diff line number Diff line
@@ -193,6 +193,10 @@ def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">; 
def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",

                                        "Disable use of the jal instruction">;



def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",

                                                    "UseIndirectJumpsHazard",

                                                    "true", "Use indirect jump"

                        " guards to prevent certain speculation based attacks">;

//===----------------------------------------------------------------------===//

// Mips processors supported.

//===----------------------------------------------------------------------===//

llvm/lib/Target/Mips/Mips32r6InstrInfo.td

+39 −0
Original line number Diff line number Diff line
@@ -1036,3 +1036,42 @@ def : MipsPat<(select i32:$cond, immz, i32:$f), 
              (SELEQZ i32:$f, i32:$cond)>,

              ISA_MIPS32R6;

}



// Pseudo instructions

let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,

    hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in {

  class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> :

    PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,

    PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>;

}



class PseudoIndirectBranchBaseR6<Instruction JumpInst, Register RT,

                                 RegisterOperand RO> :

    MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],

               II_IndirectBranchPseudo>,

    PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> {

  let isTerminator=1;

  let isBarrier=1;

  let hasDelaySlot = 1;

  let isBranch = 1;

  let isIndirectBranch = 1;

  bit isCTI = 1;

}





let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,

                            NoIndirectJumpGuards] in {

  def TAILCALLR6REG : TailCallRegR6<JALR, ZERO, GPR32Opnd>, ISA_MIPS32R6;

  def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, ZERO,

                                                          GPR32Opnd>,

                               ISA_MIPS32R6;

}



let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,

                            UseIndirectJumpsHazard] in {

  def TAILCALLHBR6REG : TailCallReg<JR_HB_R6, GPR32Opnd>, ISA_MIPS32R6;

  def PseudoIndrectHazardBranchR6 : PseudoIndirectBranchBase<JR_HB_R6,

                                                             GPR32Opnd>,

                                    ISA_MIPS32R6;

}