Commit eb7f74e3 authored by Matt Arsenault's avatar Matt Arsenault
Browse files

CodeGen: Use Register

parent c8c987d3

llvm/include/llvm/CodeGen/GlobalISel/Utils.h

+8 −8
Original line number Diff line number Diff line
@@ -42,9 +42,9 @@ class APFloat; 
/// create a new virtual register in the correct class.

///

/// \return The virtual register constrained to the right register class.

unsigned constrainRegToClass(MachineRegisterInfo &MRI,

Register constrainRegToClass(MachineRegisterInfo &MRI,

                             const TargetInstrInfo &TII,

                             const RegisterBankInfo &RBI, unsigned Reg,

                             const RegisterBankInfo &RBI, Register Reg,

                             const TargetRegisterClass &RegClass);



/// Constrain the Register operand OpIdx, so that it is now constrained to the
@@ -54,7 +54,7 @@ unsigned constrainRegToClass(MachineRegisterInfo &MRI, 
/// definition. The debug location of \p InsertPt is used for the new copy.

///

/// \return The virtual register constrained to the right register class.

unsigned constrainOperandRegClass(const MachineFunction &MF,

Register constrainOperandRegClass(const MachineFunction &MF,

                                  const TargetRegisterInfo &TRI,

                                  MachineRegisterInfo &MRI,

                                  const TargetInstrInfo &TII,
@@ -72,7 +72,7 @@ unsigned constrainOperandRegClass(const MachineFunction &MF, 
/// InsertPt is used for the new copy.

///

/// \return The virtual register constrained to the right register class.

unsigned constrainOperandRegClass(const MachineFunction &MF,

Register constrainOperandRegClass(const MachineFunction &MF,

                                  const TargetRegisterInfo &TRI,

                                  MachineRegisterInfo &MRI,

                                  const TargetInstrInfo &TII,
@@ -110,13 +110,13 @@ void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 


/// If \p VReg is defined by a G_CONSTANT fits in int64_t

/// returns it.

Optional<int64_t> getConstantVRegVal(unsigned VReg,

Optional<int64_t> getConstantVRegVal(Register VReg,

                                     const MachineRegisterInfo &MRI);

/// Simple struct used to hold a constant integer value and a virtual

/// register.

struct ValueAndVReg {

  int64_t Value;

  unsigned VReg;

  Register VReg;

};

/// If \p VReg is defined by a statically evaluable chain of

/// instructions rooted on a G_F/CONSTANT (\p LookThroughInstrs == true)
@@ -126,10 +126,10 @@ struct ValueAndVReg { 
/// getConstantVRegVal.

/// When \p HandleFConstants == false the function bails on G_FCONSTANTs.

Optional<ValueAndVReg>

getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI,

getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,

                                  bool LookThroughInstrs = true,

                                  bool HandleFConstants = true);

const ConstantFP* getConstantFPVRegVal(unsigned VReg,

const ConstantFP* getConstantFPVRegVal(Register VReg,

                                       const MachineRegisterInfo &MRI);



/// See if Reg is defined by an single def instruction that is

llvm/include/llvm/CodeGen/LiveRangeEdit.h

+1 −1
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ private: 


  /// MachineRegisterInfo callback to notify when new virtual

  /// registers are created.

  void MRI_NoteNewVirtualRegister(unsigned VReg) override;

  void MRI_NoteNewVirtualRegister(Register VReg) override;



  /// Check if MachineOperand \p MO is a last use/kill either in the

  /// main live range of \p LI or in one of the matching subregister ranges.

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

+75 −75

File changed.

Preview size limit exceeded, changes collapsed.

llvm/lib/CodeGen/GlobalISel/Utils.cpp

+8 −8
Original line number Diff line number Diff line
@@ -27,9 +27,9 @@ 


using namespace llvm;



unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,

Register llvm::constrainRegToClass(MachineRegisterInfo &MRI,

                                   const TargetInstrInfo &TII,

                                   const RegisterBankInfo &RBI, unsigned Reg,

                                   const RegisterBankInfo &RBI, Register Reg,

                                   const TargetRegisterClass &RegClass) {

  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))

    return MRI.createVirtualRegister(&RegClass);
@@ -37,7 +37,7 @@ unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI, 
  return Reg;

}



unsigned llvm::constrainOperandRegClass(

Register llvm::constrainOperandRegClass(

    const MachineFunction &MF, const TargetRegisterInfo &TRI,

    MachineRegisterInfo &MRI, const TargetInstrInfo &TII,

    const RegisterBankInfo &RBI, MachineInstr &InsertPt,
@@ -47,7 +47,7 @@ unsigned llvm::constrainOperandRegClass( 
  // Assume physical registers are properly constrained.

  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");



  unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);

  Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);

  // If we created a new virtual register because the class is not compatible

  // then create a copy between the new and the old register.

  if (ConstrainedReg != Reg) {
@@ -67,7 +67,7 @@ unsigned llvm::constrainOperandRegClass( 
  return ConstrainedReg;

}



unsigned llvm::constrainOperandRegClass(

Register llvm::constrainOperandRegClass(

    const MachineFunction &MF, const TargetRegisterInfo &TRI,

    MachineRegisterInfo &MRI, const TargetInstrInfo &TII,

    const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
@@ -204,7 +204,7 @@ void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 
  reportGISelFailure(MF, TPC, MORE, R);

}



Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,

Optional<int64_t> llvm::getConstantVRegVal(Register VReg,

                                           const MachineRegisterInfo &MRI) {

  Optional<ValueAndVReg> ValAndVReg =

      getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false);
@@ -216,7 +216,7 @@ Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg, 
}



Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough(

    unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,

    Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,

    bool HandleFConstant) {

  SmallVector<std::pair<unsigned, unsigned>, 4> SeenOpcodes;

  MachineInstr *MI;
@@ -292,7 +292,7 @@ Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough( 
  return ValueAndVReg{Val.getSExtValue(), VReg};

}



const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,

const llvm::ConstantFP* llvm::getConstantFPVRegVal(Register VReg,

                                       const MachineRegisterInfo &MRI) {

  MachineInstr *MI = MRI.getVRegDef(VReg);

  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())

llvm/lib/CodeGen/LiveRangeEdit.cpp

+1 −2
Original line number Diff line number Diff line
@@ -450,8 +450,7 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead, 
// Keep track of new virtual registers created via

// MachineRegisterInfo::createVirtualRegister.

void

LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg)

{

LiveRangeEdit::MRI_NoteNewVirtualRegister(Register VReg) {

  if (VRM)

    VRM->grow();