Commit ea6eb813 authored by Jim Lin's avatar Jim Lin
Browse files

[AVR][NFC] Use Register instead of unsigned 

Summary: Use Register type for variables instead of unsigned type.

Reviewers: dylanmckay

Reviewed By: dylanmckay

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75595
parent ffe6695a

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

+136 −136
Original line number Diff line number Diff line
@@ -51,9 +51,9 @@ private: 
  const TargetInstrInfo *TII;



  /// The register to be used for temporary storage.

  const unsigned SCRATCH_REGISTER = AVR::R0;

  const Register SCRATCH_REGISTER = AVR::R0;

  /// The register that will always contain zero.

  const unsigned ZERO_REGISTER = AVR::R1;

  const Register ZERO_REGISTER = AVR::R1;

  /// The IO address of the status register.

  const unsigned SREG_ADDR = 0x3f;
@@ -66,7 +66,7 @@ private: 
  }



  MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,

                              unsigned DstReg) {

                              Register DstReg) {

    return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);

  }
@@ -91,7 +91,7 @@ private: 
                                BlockIt MBBI);



  /// Scavenges a free GPR8 register for use.

  unsigned scavengeGPR8(MachineInstr &MI);

  Register scavengeGPR8(MachineInstr &MI);

};



char AVRExpandPseudo::ID = 0;
@@ -141,7 +141,7 @@ bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 
bool AVRExpandPseudo::

expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;

  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(2).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();
@@ -174,7 +174,7 @@ expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI) { 
bool AVRExpandPseudo::

expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;

  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(2).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();
@@ -221,7 +221,7 @@ bool AVRExpandPseudo:: 
bool AVRExpandPseudo::

expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned DstLoReg, DstHiReg;

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool SrcIsKill = MI.getOperand(1).isKill();
@@ -273,8 +273,8 @@ bool AVRExpandPseudo::expand<AVR::SUBWRdRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::SUBIWRdK>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool SrcIsKill = MI.getOperand(1).isKill();

  bool ImpIsDead = MI.getOperand(3).isDead();
@@ -325,16 +325,16 @@ bool AVRExpandPseudo::expand<AVR::SBCWRdRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::SBCIWRdK>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool SrcIsKill = MI.getOperand(1).isKill();

  bool ImpIsDead = MI.getOperand(3).isDead();

  unsigned Imm = MI.getOperand(2).getImm();

  unsigned Lo8 = Imm & 0xff;

  unsigned Hi8 = (Imm >> 8) & 0xff;

  OpLo = AVR::SBCIRdK;

  OpHi = AVR::SBCIRdK;

  unsigned OpLo = AVR::SBCIRdK;

  unsigned OpHi = AVR::SBCIRdK;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  auto MIBLO = buildMI(MBB, MBBI, OpLo)
@@ -388,13 +388,13 @@ bool AVRExpandPseudo::expand<AVR::EORWRdRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool DstIsKill = MI.getOperand(1).isKill();

  bool ImpIsDead = MI.getOperand(2).isDead();

  OpLo = AVR::COMRd;

  OpHi = AVR::COMRd;

  unsigned OpLo = AVR::COMRd;

  unsigned OpHi = AVR::COMRd;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  auto MIBLO = buildMI(MBB, MBBI, OpLo)
@@ -418,14 +418,14 @@ bool AVRExpandPseudo::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(1).getReg();

  bool DstIsKill = MI.getOperand(0).isKill();

  bool SrcIsKill = MI.getOperand(1).isKill();

  bool ImpIsDead = MI.getOperand(2).isDead();

  OpLo = AVR::CPRdRr;

  OpHi = AVR::CPCRdRr;

  unsigned OpLo = AVR::CPRdRr;

  unsigned OpHi = AVR::CPCRdRr;

  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
@@ -451,14 +451,14 @@ bool AVRExpandPseudo::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(1).getReg();

  bool DstIsKill = MI.getOperand(0).isKill();

  bool SrcIsKill = MI.getOperand(1).isKill();

  bool ImpIsDead = MI.getOperand(2).isDead();

  OpLo = AVR::CPCRdRr;

  OpHi = AVR::CPCRdRr;

  unsigned OpLo = AVR::CPCRdRr;

  unsigned OpHi = AVR::CPCRdRr;

  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
@@ -486,11 +486,11 @@ bool AVRExpandPseudo::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  OpLo = AVR::LDIRdK;

  OpHi = AVR::LDIRdK;

  unsigned OpLo = AVR::LDIRdK;

  unsigned OpHi = AVR::LDIRdK;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  auto MIBLO = buildMI(MBB, MBBI, OpLo)
@@ -535,11 +535,11 @@ bool AVRExpandPseudo::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  OpLo = AVR::LDSRdK;

  OpHi = AVR::LDSRdK;

  unsigned OpLo = AVR::LDSRdK;

  unsigned OpHi = AVR::LDSRdK;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  auto MIBLO = buildMI(MBB, MBBI, OpLo)
@@ -579,21 +579,21 @@ bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned TmpReg = 0; // 0 for no temporary register

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register TmpReg = 0; // 0 for no temporary register

  Register SrcReg = MI.getOperand(1).getReg();

  bool SrcIsKill = MI.getOperand(1).isKill();

  OpLo = AVR::LDRdPtr;

  OpHi = AVR::LDDRdPtrQ;

  unsigned OpLo = AVR::LDRdPtr;

  unsigned OpHi = AVR::LDDRdPtrQ;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  // Use a temporary register if src and dst registers are the same.

  if (DstReg == SrcReg)

    TmpReg = scavengeGPR8(MI);



  unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;

  unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;

  Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;

  Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;



  // Load low byte.

  auto MIBLO = buildMI(MBB, MBBI, OpLo)
@@ -628,13 +628,13 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(1).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool SrcIsDead = MI.getOperand(1).isKill();

  OpLo = AVR::LDRdPtrPi;

  OpHi = AVR::LDRdPtrPi;

  unsigned OpLo = AVR::LDRdPtrPi;

  unsigned OpHi = AVR::LDRdPtrPi;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
@@ -659,13 +659,13 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(1).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool SrcIsDead = MI.getOperand(1).isKill();

  OpLo = AVR::LDRdPtrPd;

  OpHi = AVR::LDRdPtrPd;

  unsigned OpLo = AVR::LDRdPtrPd;

  unsigned OpHi = AVR::LDRdPtrPd;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
@@ -690,14 +690,14 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned TmpReg = 0; // 0 for no temporary register

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register TmpReg = 0; // 0 for no temporary register

  Register SrcReg = MI.getOperand(1).getReg();

  unsigned Imm = MI.getOperand(2).getImm();

  bool SrcIsKill = MI.getOperand(1).isKill();

  OpLo = AVR::LDDRdPtrQ;

  OpHi = AVR::LDDRdPtrQ;

  unsigned OpLo = AVR::LDDRdPtrQ;

  unsigned OpHi = AVR::LDDRdPtrQ;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
@@ -708,8 +708,8 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) { 
  if (DstReg == SrcReg)

    TmpReg = scavengeGPR8(MI);



  unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;

  unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;

  Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;

  Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;



  // Load low byte.

  auto MIBLO = buildMI(MBB, MBBI, OpLo)
@@ -745,21 +745,21 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned TmpReg = 0; // 0 for no temporary register

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register TmpReg = 0; // 0 for no temporary register

  Register SrcReg = MI.getOperand(1).getReg();

  bool SrcIsKill = MI.getOperand(1).isKill();

  OpLo = AVR::LPMRdZPi;

  OpHi = AVR::LPMRdZ;

  unsigned OpLo = AVR::LPMRdZPi;

  unsigned OpHi = AVR::LPMRdZ;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  // Use a temporary register if src and dst registers are the same.

  if (DstReg == SrcReg)

    TmpReg = scavengeGPR8(MI);



  unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;

  unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;

  Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;

  Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;



  // Load low byte.

  auto MIBLO = buildMI(MBB, MBBI, OpLo)
@@ -862,7 +862,7 @@ bool AVRExpandPseudo::expandAtomicArithmeticOp(unsigned Width, 
  });

}



unsigned AVRExpandPseudo::scavengeGPR8(MachineInstr &MI) {

Register AVRExpandPseudo::scavengeGPR8(MachineInstr &MI) {

  MachineBasicBlock &MBB = *MI.getParent();

  RegScavenger RS;
@@ -968,11 +968,11 @@ bool AVRExpandPseudo::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register SrcLoReg, SrcHiReg;

  Register SrcReg = MI.getOperand(1).getReg();

  bool SrcIsKill = MI.getOperand(1).isKill();

  OpLo = AVR::STSKRr;

  OpHi = AVR::STSKRr;

  unsigned OpLo = AVR::STSKRr;

  unsigned OpHi = AVR::STSKRr;

  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);



  // Write the high byte first in case this address belongs to a special
@@ -1014,12 +1014,12 @@ bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register SrcLoReg, SrcHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(1).getReg();

  bool SrcIsKill = MI.getOperand(1).isKill();

  OpLo = AVR::STPtrRr;

  OpHi = AVR::STDPtrQRr;

  unsigned OpLo = AVR::STPtrRr;

  unsigned OpHi = AVR::STDPtrQRr;

  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);



  //:TODO: need to reverse this order like inw and stsw?
@@ -1042,14 +1042,14 @@ bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned SrcReg = MI.getOperand(2).getReg();

  Register SrcLoReg, SrcHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(2).getReg();

  unsigned Imm = MI.getOperand(3).getImm();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool SrcIsKill = MI.getOperand(2).isKill();

  OpLo = AVR::STPtrPiRr;

  OpHi = AVR::STPtrPiRr;

  unsigned OpLo = AVR::STPtrPiRr;

  unsigned OpHi = AVR::STPtrPiRr;

  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);



  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
@@ -1076,14 +1076,14 @@ bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned SrcReg = MI.getOperand(2).getReg();

  Register SrcLoReg, SrcHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(2).getReg();

  unsigned Imm = MI.getOperand(3).getImm();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool SrcIsKill = MI.getOperand(2).isKill();

  OpLo = AVR::STPtrPdRr;

  OpHi = AVR::STPtrPdRr;

  unsigned OpLo = AVR::STPtrPdRr;

  unsigned OpHi = AVR::STPtrPdRr;

  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);



  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
@@ -1110,14 +1110,14 @@ bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned SrcReg = MI.getOperand(2).getReg();

  Register SrcLoReg, SrcHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(2).getReg();

  unsigned Imm = MI.getOperand(1).getImm();

  bool DstIsKill = MI.getOperand(0).isKill();

  bool SrcIsKill = MI.getOperand(2).isKill();

  OpLo = AVR::STDPtrQRr;

  OpHi = AVR::STDPtrQRr;

  unsigned OpLo = AVR::STDPtrQRr;

  unsigned OpHi = AVR::STDPtrQRr;

  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);



  // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
@@ -1144,12 +1144,12 @@ bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  Register DstLoReg, DstHiReg;

  unsigned Imm = MI.getOperand(1).getImm();

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  OpLo = AVR::INRdA;

  OpHi = AVR::INRdA;

  unsigned OpLo = AVR::INRdA;

  unsigned OpHi = AVR::INRdA;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
@@ -1174,12 +1174,12 @@ bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;

  Register SrcLoReg, SrcHiReg;

  unsigned Imm = MI.getOperand(0).getImm();

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register SrcReg = MI.getOperand(1).getReg();

  bool SrcIsKill = MI.getOperand(1).isKill();

  OpLo = AVR::OUTARr;

  OpHi = AVR::OUTARr;

  unsigned OpLo = AVR::OUTARr;

  unsigned OpHi = AVR::OUTARr;

  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);



  // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
@@ -1205,12 +1205,12 @@ bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, SrcLoReg, SrcHiReg;

  unsigned SrcReg = MI.getOperand(0).getReg();

  Register SrcLoReg, SrcHiReg;

  Register SrcReg = MI.getOperand(0).getReg();

  bool SrcIsKill = MI.getOperand(0).isKill();

  unsigned Flags = MI.getFlags();

  OpLo = AVR::PUSHRr;

  OpHi = AVR::PUSHRr;

  unsigned OpLo = AVR::PUSHRr;

  unsigned OpHi = AVR::PUSHRr;

  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);



  // Low part
@@ -1230,11 +1230,11 @@ bool AVRExpandPseudo::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  unsigned Flags = MI.getFlags();

  OpLo = AVR::POPRd;

  OpHi = AVR::POPRd;

  unsigned OpLo = AVR::POPRd;

  unsigned OpHi = AVR::POPRd;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
@@ -1254,7 +1254,7 @@ bool AVRExpandPseudo::expand<AVR::ROLBRd>(Block &MBB, BlockIt MBBI) { 


  MachineInstr &MI = *MBBI;

  unsigned OpShift, OpCarry;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  OpShift = AVR::ADDRdRr;

  OpCarry = AVR::ADCRdRr;
@@ -1291,7 +1291,7 @@ bool AVRExpandPseudo::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) { 


  MachineInstr &MI = *MBBI;

  unsigned OpShiftOut, OpLoad, OpShiftIn, OpAdd;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  OpShiftOut = AVR::LSRRd;

  OpLoad = AVR::LDIRdK;
@@ -1334,13 +1334,13 @@ bool AVRExpandPseudo::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool DstIsKill = MI.getOperand(1).isKill();

  bool ImpIsDead = MI.getOperand(2).isDead();

  OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd

  OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd

  unsigned OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd

  unsigned OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  // Low part
@@ -1367,13 +1367,13 @@ bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool DstIsKill = MI.getOperand(1).isKill();

  bool ImpIsDead = MI.getOperand(2).isDead();

  OpLo = AVR::RORRd;

  OpHi = AVR::LSRRd;

  unsigned OpLo = AVR::RORRd;

  unsigned OpHi = AVR::LSRRd;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  // High part
@@ -1410,13 +1410,13 @@ bool AVRExpandPseudo::expand<AVR::ROLWRd>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool DstIsKill = MI.getOperand(1).isKill();

  bool ImpIsDead = MI.getOperand(2).isDead();

  OpLo = AVR::RORRd;

  OpHi = AVR::ASRRd;

  unsigned OpLo = AVR::RORRd;

  unsigned OpHi = AVR::ASRRd;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  // High part
@@ -1440,7 +1440,7 @@ bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) { 


template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned DstLoReg, DstHiReg;

  Register DstLoReg, DstHiReg;

  // sext R17:R16, R17

  // mov     r16, r17

  // lsl     r17
@@ -1454,8 +1454,8 @@ template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) { 
  // mov     r17, r16

  // lsl     r17

  // sbc     r17, r17

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(1).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool SrcIsKill = MI.getOperand(1).isKill();

  bool ImpIsDead = MI.getOperand(2).isDead();
@@ -1499,7 +1499,7 @@ template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) { 


template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned DstLoReg, DstHiReg;

  Register DstLoReg, DstHiReg;

  // zext R25:R24, R20

  // mov      R24, R20

  // eor      R25, R25
@@ -1508,8 +1508,8 @@ template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) { 
  // zext R25:R24, R25

  // mov      R24, R25

  // eor      R25, R25

  unsigned DstReg = MI.getOperand(0).getReg();

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(1).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  bool SrcIsKill = MI.getOperand(1).isKill();

  bool ImpIsDead = MI.getOperand(2).isDead();
@@ -1536,12 +1536,12 @@ template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned OpLo, OpHi, DstLoReg, DstHiReg;

  unsigned DstReg = MI.getOperand(0).getReg();

  Register DstLoReg, DstHiReg;

  Register DstReg = MI.getOperand(0).getReg();

  bool DstIsDead = MI.getOperand(0).isDead();

  unsigned Flags = MI.getFlags();

  OpLo = AVR::INRdA;

  OpHi = AVR::INRdA;

  unsigned OpLo = AVR::INRdA;

  unsigned OpHi = AVR::INRdA;

  TRI->splitReg(DstReg, DstLoReg, DstHiReg);



  // Low part
@@ -1563,8 +1563,8 @@ bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) { 
template <>

bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {

  MachineInstr &MI = *MBBI;

  unsigned SrcLoReg, SrcHiReg;

  unsigned SrcReg = MI.getOperand(1).getReg();

  Register SrcLoReg, SrcHiReg;

  Register SrcReg = MI.getOperand(1).getReg();

  bool SrcIsKill = MI.getOperand(1).isKill();

  unsigned Flags = MI.getFlags();

  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);

llvm/lib/Target/AVR/AVRFrameLowering.cpp

+1 −1
Original line number Diff line number Diff line
@@ -507,7 +507,7 @@ struct AVRDynAllocaSR : public MachineFunctionPass { 
    MachineBasicBlock::iterator MBBI = EntryMBB.begin();

    DebugLoc DL = EntryMBB.findDebugLoc(MBBI);



    unsigned SPCopy =

    Register SPCopy =

        MF.getRegInfo().createVirtualRegister(&AVR::DREGSRegClass);



    // Create a copy of SP in function entry before any dynallocas are

llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

+2 −2
Original line number Diff line number Diff line
@@ -265,7 +265,7 @@ bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, 
      if (RI.getRegClass(Reg) != &AVR::PTRDISPREGSRegClass) {

        SDLoc dl(CopyFromRegOp);



        unsigned VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass);

        Register VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass);



        SDValue CopyToReg =

            CurDAG->getCopyToReg(CopyFromRegOp, dl, VReg, CopyFromRegOp);
@@ -294,7 +294,7 @@ bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, 
  // More generic case.

  // Create chain that puts Op into pointer register

  // and return that register.

  unsigned VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass);

  Register VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass);



  SDValue CopyToReg = CurDAG->getCopyToReg(Op, dl, VReg, Op);

  SDValue CopyFromReg =

llvm/lib/Target/AVR/AVRISelLowering.cpp

+2 −2
Original line number Diff line number Diff line
@@ -1516,8 +1516,8 @@ MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI, 
  LoopBB->addSuccessor(RemBB);

  LoopBB->addSuccessor(LoopBB);



  unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);

  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);

  Register ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);

  Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);

  Register ShiftReg = RI.createVirtualRegister(RC);

  Register ShiftReg2 = RI.createVirtualRegister(RC);

  Register ShiftAmtSrcReg = MI.getOperand(2).getReg();

llvm/lib/Target/AVR/AVRInstrInfo.cpp

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 
      BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)

          .addReg(SrcReg, getKillRegState(KillSrc));

    } else {

      unsigned DestLo, DestHi, SrcLo, SrcHi;

      Register DestLo, DestHi, SrcLo, SrcHi;



      TRI.splitReg(DestReg, DestLo, DestHi);

      TRI.splitReg(SrcReg,  SrcLo,  SrcHi);