Commit e0ab0e6a authored by Simon Atanasyan's avatar Simon Atanasyan
Browse files

[MIPS] Implement PUL.PS and PUU.PS instructions 

Patch by Michael Roe.

Differential Revision: https://reviews.llvm.org/D75812
parent ad643d5e

llvm/lib/Target/Mips/MipsInstrFPU.td

+6 −0
Original line number Diff line number Diff line
@@ -456,6 +456,12 @@ let DecoderNamespace = "MipsFP64" in { 
    def PLU_PS64    : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>,

                      ADDS_FM<0x2D, 22>,

                      ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;

    def PUL_PS64    : ADDS_FT<"pul.ps", FGR64Opnd, II_CVT, 0>,

                      ADDS_FM<0x2E, 22>,

                      ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;

    def PUU_PS64    : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>,

                      ADDS_FM<0x2F, 22>,

                      ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;



    def CVT_S_PU64  : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,

                      ABSS_FM<0x20, 22>,

llvm/lib/Target/Mips/MipsScheduleGeneric.td

+1 −1
Original line number Diff line number Diff line
@@ -832,7 +832,7 @@ def : InstRW<[GenericWriteFPUL], (instrs CEIL_L_D64, CEIL_L_S, CEIL_W_D32, 
                                  FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64,

                                  MADD_D32, MADD_D64, MSUB_D32, MSUB_D64,

                                  NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64,

                                  PLL_PS64, PLU_PS64,

                                  PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64,

                                  ROUND_L_D64, ROUND_L_S, ROUND_W_D32,

                                  ROUND_W_D64, ROUND_W_S, TRUNC_L_D64,

                                  TRUNC_L_S, TRUNC_W_D32, TRUNC_W_D64,

llvm/lib/Target/Mips/MipsScheduleP5600.td

+1 −1
Original line number Diff line number Diff line
@@ -457,7 +457,7 @@ def : InstRW<[P5600WriteFPUL], (instrs CVT_PS_S64, CVT_S_PL64, CVT_S_PU64)>; 
def : InstRW<[P5600WriteFPUL], (instregex "^C_[A-Z]+_(S|D32|D64)$")>;

def : InstRW<[P5600WriteFPUL], (instregex "^FCMP_(S32|D32|D64)$")>;

def : InstRW<[P5600WriteFPUL], (instregex "^PseudoCVT_(S|D32|D64)_(L|W)$")>;

def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64)>;

def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64)>;



// div.[ds], div.ps

def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>;

llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s

+0 −2
Original line number Diff line number Diff line
@@ -36,8 +36,6 @@ 
        neg.ps    $f19,$f13           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

        nmadd.ps  $f27,$f4,$f9,$f25   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

        nmsub.ps  $f6,$f12,$f14,$f17  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

        pul.ps    $f9,$f30,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

        puu.ps    $f24,$f9,$f2        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

        sub.ps    $f5,$f14,$f26       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

        c.eq.s    $fcc1, $f2, $f8     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level

        c.f.s     $fcc4, $f2, $f7     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level

llvm/test/MC/Mips/mips1/invalid-mips5.s

+2 −0
Original line number Diff line number Diff line
@@ -73,6 +73,8 @@ 
        movz.s    $f25,$f7,$v1      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

        pll.ps    $f25,$f9,$f30     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

        plu.ps    $f1,$f26,$f29     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

        pul.ps    $f9,$f30,$f26     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

        puu.ps    $f24,$f9,$f2      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

        round.l.d $f12,$f1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

        round.l.s $f25,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

        round.w.d $f6,$f4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled