Commit df0cc105 authored by David Tellenbach's avatar David Tellenbach
Browse files

Reland [AArch64][MachineOutliner] Return address signing for outlined functions 

Summary:
Reland after fixing a bug that allowed outlining of SP modifying instructions
that invalidated return address signing.

During AArch64 frame lowering instructions to enable return address
signing are inserted into functions if needed. Functions generated during
machine outlining don't run through target frame lowering and hence are
missing such instructions.

This patch introduces the following changes:

1. If not all functions that potentially participate in function outlining agree
   on their return address signing scope and their return address signing key,
   outlining is disabled for these functions.
2. If not all functions that potentially participate in function outlining agree
   on their support for v8.3A features, outlining is disabled for these
   functions.
3. If an outlining candidate would outline instructions that modify sp in a way
   that invalidates return address signing, outlining is disabled for that
   particular candidate.
4. If all candidate functions agree on the signing scope, signing key and their
   support for v8.3 features, the outlined function behaves as if it had the
   same scope and key attributes and as if it would provide the same v8.3A
   support as the original functions.

Reviewers: ostannard, paquette

Reviewed By: ostannard

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70635
parent 9d3f4a49

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

+304 −8
Original line number Diff line number Diff line
@@ -5483,8 +5483,99 @@ AArch64InstrInfo::findRegisterToSaveLRTo(const outliner::Candidate &C) const { 
  return 0u;

}



outliner::OutlinedFunction

AArch64InstrInfo::getOutliningCandidateInfo(

static bool

outliningCandidatesSigningScopeConsensus(const outliner::Candidate &a,

                                         const outliner::Candidate &b) {

  const Function &Fa = a.getMF()->getFunction();

  const Function &Fb = b.getMF()->getFunction();



  // If none of the functions have the "sign-return-address" attribute their

  // signing behaviour is equal

  if (!Fa.hasFnAttribute("sign-return-address") &&

      !Fb.hasFnAttribute("sign-return-address")) {

    return true;

  }



  // If both functions have the "sign-return-address" attribute their signing

  // behaviour is equal, if the values of the attributes are equal

  if (Fa.hasFnAttribute("sign-return-address") &&

      Fb.hasFnAttribute("sign-return-address")) {

    StringRef ScopeA =

        Fa.getFnAttribute("sign-return-address").getValueAsString();

    StringRef ScopeB =

        Fb.getFnAttribute("sign-return-address").getValueAsString();

    return ScopeA.equals(ScopeB);

  }



  // If function B doesn't have the "sign-return-address" attribute but A does,

  // the functions' signing behaviour is equal if A's value for

  // "sign-return-address" is "none" and vice versa.

  if (Fa.hasFnAttribute("sign-return-address")) {

    StringRef ScopeA =

        Fa.getFnAttribute("sign-return-address").getValueAsString();

    return ScopeA.equals("none");

  }



  if (Fb.hasFnAttribute("sign-return-address")) {

    StringRef ScopeB =

        Fb.getFnAttribute("sign-return-address").getValueAsString();

    return ScopeB.equals("none");

  }



  llvm_unreachable("Unkown combination of sign-return-address attributes");

}



static bool

outliningCandidatesSigningKeyConsensus(const outliner::Candidate &a,

                                       const outliner::Candidate &b) {

  const Function &Fa = a.getMF()->getFunction();

  const Function &Fb = b.getMF()->getFunction();



  // If none of the functions have the "sign-return-address-key" attribute

  // their keys are equal

  if (!Fa.hasFnAttribute("sign-return-address-key") &&

      !Fb.hasFnAttribute("sign-return-address-key")) {

    return true;

  }



  // If both functions have the "sign-return-address-key" attribute their

  // keys are equal if the values of "sign-return-address-key" are equal

  if (Fa.hasFnAttribute("sign-return-address-key") &&

      Fb.hasFnAttribute("sign-return-address-key")) {

    StringRef KeyA =

        Fa.getFnAttribute("sign-return-address-key").getValueAsString();

    StringRef KeyB =

        Fb.getFnAttribute("sign-return-address-key").getValueAsString();

    return KeyA.equals(KeyB);

  }



  // If B doesn't have the "sign-return-address-key" attribute, both keys are

  // equal, if function a has the default key (a_key)

  if (Fa.hasFnAttribute("sign-return-address-key")) {

    StringRef KeyA =

        Fa.getFnAttribute("sign-return-address-key").getValueAsString();

    return KeyA.equals_lower("a_key");

  }



  if (Fb.hasFnAttribute("sign-return-address-key")) {

    StringRef KeyB =

        Fb.getFnAttribute("sign-return-address-key").getValueAsString();

    return KeyB.equals_lower("a_key");

  }



  llvm_unreachable("Unkown combination of sign-return-address-key attributes");

}



static bool outliningCandidatesV8_3OpsConsensus(const outliner::Candidate &a,

                                                const outliner::Candidate &b) {

  const AArch64Subtarget &SubtargetA =

      a.getMF()->getSubtarget<AArch64Subtarget>();

  const AArch64Subtarget &SubtargetB =

      b.getMF()->getSubtarget<AArch64Subtarget>();

  return SubtargetA.hasV8_3aOps() == SubtargetB.hasV8_3aOps();

}



outliner::OutlinedFunction AArch64InstrInfo::getOutliningCandidateInfo(

    std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {

  outliner::Candidate &FirstCand = RepeatedSequenceLocs[0];

  unsigned SequenceSize =
@@ -5492,12 +5583,115 @@ AArch64InstrInfo::getOutliningCandidateInfo( 
                      [this](unsigned Sum, const MachineInstr &MI) {

                        return Sum + getInstSizeInBytes(MI);

                      });

  unsigned NumBytesToCreateFrame = 0;



  // We only allow outlining for functions having exactly matching return

  // address signing attributes, i.e., all share the same value for the

  // attribute "sign-return-address" and all share the same type of key they

  // are signed with.

  // Additionally we require all functions to simultaniously either support

  // v8.3a features or not. Otherwise an outlined function could get signed

  // using dedicated v8.3 instructions and a call from a function that doesn't

  // support v8.3 instructions would therefore be invalid.

  if (std::adjacent_find(

          RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),

          [](const outliner::Candidate &a, const outliner::Candidate &b) {

            // Return true if a and b are non-equal w.r.t. return address

            // signing or support of v8.3a features

            if (outliningCandidatesSigningScopeConsensus(a, b) &&

                outliningCandidatesSigningKeyConsensus(a, b) &&

                outliningCandidatesV8_3OpsConsensus(a, b)) {

              return false;

            }

            return true;

          }) != RepeatedSequenceLocs.end()) {

    return outliner::OutlinedFunction();

  }



  // Since at this point all candidates agree on their return address signing

  // picking just one is fine. If the candidate functions potentially sign their

  // return addresses, the outlined function should do the same. Note that in

  // the case of "sign-return-address"="non-leaf" this is an assumption: It is

  // not certainly true that the outlined function will have to sign its return

  // address but this decision is made later, when the decision to outline

  // has already been made.

  // The same holds for the number of additional instructions we need: On

  // v8.3a RET can be replaced by RETAA/RETAB and no AUT instruction is

  // necessary. However, at this point we don't know if the outlined function

  // will have a RET instruction so we assume the worst.

  const Function &FCF = FirstCand.getMF()->getFunction();

  const TargetRegisterInfo &TRI = getRegisterInfo();

  if (FCF.hasFnAttribute("sign-return-address")) {

    // One PAC and one AUT instructions

    NumBytesToCreateFrame += 8;



    // We have to check if sp modifying instructions would get outlined.

    // If so we only allow outlining if sp is unchanged overall, so matching

    // sub and add instructions are okay to outline, all other sp modifications

    // are not

    auto hasIllegalSPModification = [&TRI](outliner::Candidate &C) {

      int SPValue = 0;

      MachineBasicBlock::iterator MBBI = C.front();

      for (;;) {

        if (MBBI->modifiesRegister(AArch64::SP, &TRI)) {

          switch (MBBI->getOpcode()) {

          case AArch64::ADDXri:

          case AArch64::ADDWri:

            assert(MBBI->getNumOperands() == 4 && "Wrong number of operands");

            assert(MBBI->getOperand(2).isImm() &&

                   "Expected operand to be immediate");

            assert(MBBI->getOperand(1).isReg() &&

                   "Expected operand to be a register");

            // Check if the add just increments sp. If so, we search for

            // matching sub instructions that decrement sp. If not, the

            // modification is illegal

            if (MBBI->getOperand(1).getReg() == AArch64::SP)

              SPValue += MBBI->getOperand(2).getImm();

            else

              return true;

            break;

          case AArch64::SUBXri:

          case AArch64::SUBWri:

            assert(MBBI->getNumOperands() == 4 && "Wrong number of operands");

            assert(MBBI->getOperand(2).isImm() &&

                   "Expected operand to be immediate");

            assert(MBBI->getOperand(1).isReg() &&

                   "Expected operand to be a register");

            // Check if the sub just decrements sp. If so, we search for

            // matching add instructions that increment sp. If not, the

            // modification is illegal

            if (MBBI->getOperand(1).getReg() == AArch64::SP)

              SPValue -= MBBI->getOperand(2).getImm();

            else

              return true;

            break;

          default:

            return true;

          }

        }

        if (MBBI == C.back())

          break;

        ++MBBI;

      }

      if (SPValue)

        return true;

      return false;

    };

    // Remove candidates with illegal stack modifying instructions

    RepeatedSequenceLocs.erase(std::remove_if(RepeatedSequenceLocs.begin(),

                                              RepeatedSequenceLocs.end(),

                                              hasIllegalSPModification),

                               RepeatedSequenceLocs.end());



    // If the sequence doesn't have enough candidates left, then we're done.

    if (RepeatedSequenceLocs.size() < 2)

      return outliner::OutlinedFunction();

  }



  // Properties about candidate MBBs that hold for all of them.

  unsigned FlagsSetInAll = 0xF;



  // Compute liveness information for each candidate, and set FlagsSetInAll.

  const TargetRegisterInfo &TRI = getRegisterInfo();

  std::for_each(RepeatedSequenceLocs.begin(), RepeatedSequenceLocs.end(),

                [&FlagsSetInAll](outliner::Candidate &C) {

                  FlagsSetInAll &= C.Flags;
@@ -5553,7 +5747,7 @@ AArch64InstrInfo::getOutliningCandidateInfo( 
      };



  unsigned FrameID = MachineOutlinerDefault;

  unsigned NumBytesToCreateFrame = 4;

  NumBytesToCreateFrame += 4;



  bool HasBTI = any_of(RepeatedSequenceLocs, [](outliner::Candidate &C) {

    return C.getMF()->getFunction().hasFnAttribute("branch-target-enforcement");
@@ -5822,6 +6016,19 @@ AArch64InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, 
  MachineFunction *MF = MBB->getParent();

  AArch64FunctionInfo *FuncInfo = MF->getInfo<AArch64FunctionInfo>();



  // Don't outline anything used for return address signing. The outlined

  // function will get signed later if needed

  switch (MI.getOpcode()) {

  case AArch64::PACIASP:

  case AArch64::PACIBSP:

  case AArch64::AUTIASP:

  case AArch64::AUTIBSP:

  case AArch64::RETAA:

  case AArch64::RETAB:

  case AArch64::EMITBKEY:

    return outliner::InstrType::Illegal;

  }



  // Don't outline LOHs.

  if (FuncInfo->getLOHRelated().count(&MI))

    return outliner::InstrType::Illegal;
@@ -5974,6 +6181,59 @@ void AArch64InstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const { 
  }

}



static void signOutlinedFunction(MachineFunction &MF, MachineBasicBlock &MBB,

                                 bool ShouldSignReturnAddr,

                                 bool ShouldSignReturnAddrWithAKey) {

  if (ShouldSignReturnAddr) {

    MachineBasicBlock::iterator MBBPAC = MBB.begin();

    MachineBasicBlock::iterator MBBAUT = MBB.getFirstTerminator();

    const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();

    const TargetInstrInfo *TII = Subtarget.getInstrInfo();

    DebugLoc DL;



    if (MBBAUT != MBB.end())

      DL = MBBAUT->getDebugLoc();



    // At the very beginning of the basic block we insert the following

    // depending on the key type

    //

    // a_key:                   b_key:

    //    PACIASP                   EMITBKEY

    //    CFI_INSTRUCTION           PACIBSP

    //                              CFI_INSTRUCTION

    if (ShouldSignReturnAddrWithAKey) {

      BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::PACIASP))

          .setMIFlag(MachineInstr::FrameSetup);

    } else {

      BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::EMITBKEY))

          .setMIFlag(MachineInstr::FrameSetup);

      BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::PACIBSP))

          .setMIFlag(MachineInstr::FrameSetup);

    }

    unsigned CFIIndex =

        MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));

    BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::CFI_INSTRUCTION))

        .addCFIIndex(CFIIndex)

        .setMIFlags(MachineInstr::FrameSetup);



    // If v8.3a features are available we can replace a RET instruction by

    // RETAA or RETAB and omit the AUT instructions

    if (Subtarget.hasV8_3aOps() && MBBAUT != MBB.end() &&

        MBBAUT->getOpcode() == AArch64::RET) {

      BuildMI(MBB, MBBAUT, DL,

              TII->get(ShouldSignReturnAddrWithAKey ? AArch64::RETAA

                                                    : AArch64::RETAB))

          .copyImplicitOps(*MBBAUT);

      MBB.erase(MBBAUT);

    } else {

      BuildMI(MBB, MBBAUT, DL,

              TII->get(ShouldSignReturnAddrWithAKey ? AArch64::AUTIASP

                                                    : AArch64::AUTIBSP))

          .setMIFlag(MachineInstr::FrameDestroy);

    }

  }

}



void AArch64InstrInfo::buildOutlinedFrame(

    MachineBasicBlock &MBB, MachineFunction &MF,

    const outliner::OutlinedFunction &OF) const {
@@ -5995,10 +6255,13 @@ void AArch64InstrInfo::buildOutlinedFrame( 
    Call->eraseFromParent();

  }



  bool IsLeafFunction = true;



  // Is there a call in the outlined range?

  auto IsNonTailCall = [](MachineInstr &MI) {

  auto IsNonTailCall = [](const MachineInstr &MI) {

    return MI.isCall() && !MI.isReturn();

  };



  if (std::any_of(MBB.instr_begin(), MBB.instr_end(), IsNonTailCall)) {

    // Fix up the instructions in the range, since we're going to modify the

    // stack.
@@ -6006,6 +6269,8 @@ void AArch64InstrInfo::buildOutlinedFrame( 
           "Can only fix up stack references once");

    fixupPostOutline(MBB);



    IsLeafFunction = false;



    // LR has to be a live in so that we can save it.

    MBB.addLiveIn(AArch64::LR);
@@ -6052,16 +6317,47 @@ void AArch64InstrInfo::buildOutlinedFrame( 
    Et = MBB.insert(Et, LDRXpost);

  }



  // If a bunch of candidates reach this point they must agree on their return

  // address signing. It is therefore enough to just consider the signing

  // behaviour of one of them

  const Function &CF = OF.Candidates.front().getMF()->getFunction();

  bool ShouldSignReturnAddr = false;

  if (CF.hasFnAttribute("sign-return-address")) {

    StringRef Scope =

        CF.getFnAttribute("sign-return-address").getValueAsString();

    if (Scope.equals("all"))

      ShouldSignReturnAddr = true;

    else if (Scope.equals("non-leaf") && !IsLeafFunction)

      ShouldSignReturnAddr = true;

  }



  // a_key is the default

  bool ShouldSignReturnAddrWithAKey = true;

  if (CF.hasFnAttribute("sign-return-address-key")) {

    const StringRef Key =

        CF.getFnAttribute("sign-return-address-key").getValueAsString();

    // Key can either be a_key or b_key

    assert((Key.equals_lower("a_key") || Key.equals_lower("b_key")) &&

           "Return address signing key must be either a_key or b_key");

    ShouldSignReturnAddrWithAKey = Key.equals_lower("a_key");

  }



  // If this is a tail call outlined function, then there's already a return.

  if (OF.FrameConstructionID == MachineOutlinerTailCall ||

      OF.FrameConstructionID == MachineOutlinerThunk)

      OF.FrameConstructionID == MachineOutlinerThunk) {

    signOutlinedFunction(MF, MBB, ShouldSignReturnAddr,

                         ShouldSignReturnAddrWithAKey);

    return;

  }



  // It's not a tail call, so we have to insert the return ourselves.

  MachineInstr *ret = BuildMI(MF, DebugLoc(), get(AArch64::RET))

                          .addReg(AArch64::LR, RegState::Undef);

  MBB.insert(MBB.end(), ret);



  signOutlinedFunction(MF, MBB, ShouldSignReturnAddr,

                       ShouldSignReturnAddrWithAKey);



  // Did we have to modify the stack by saving the link register?

  if (OF.FrameConstructionID != MachineOutlinerDefault)

    return;

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll

0 → 100644
+80 −0
Original line number Diff line number Diff line 
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \

; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s



; Function a's outlining candidate contains a sp modifying add without a

; corresponsing sub, so we shouldn't outline it.

define void @a() "sign-return-address"="all" "sign-return-address-key"="b_key" {

; CHECK-LABEL:      a:                                     // @a

; CHECK:            // %bb.0:

; CHECK-NEXT:           .cfi_b_key_frame

; CHECK-NEXT:           pacibsp

; CHECK-NEXT:           .cfi_negate_ra_state

  %1 = alloca i32, align 4

  %2 = alloca i32, align 4

  %3 = alloca i32, align 4

  %4 = alloca i32, align 4

  %5 = alloca i32, align 4

  %6 = alloca i32, align 4

  store i32 1, i32* %1, align 4

  store i32 2, i32* %2, align 4

  store i32 3, i32* %3, align 4

  store i32 4, i32* %4, align 4

  store i32 5, i32* %5, align 4

  store i32 6, i32* %6, align 4

; CHECK-NOT:          bl OUTLINED_FUNCTION_{{[0-9]+}}

; CHECK:              autibsp

; CECK-NEXT:          ret

  ret void

}



define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" nounwind {

; CHECK-LABEL:      b:                                     // @b

; CHECK-NEXT:       // %bb.0:

; CHECK-NEXT:           pacibsp

  %1 = alloca i32, align 4

  %2 = alloca i32, align 4

  %3 = alloca i32, align 4

  %4 = alloca i32, align 4

  %5 = alloca i32, align 4

  %6 = alloca i32, align 4

  store i32 1, i32* %1, align 4

  store i32 2, i32* %2, align 4

  store i32 3, i32* %3, align 4

  store i32 4, i32* %4, align 4

  store i32 5, i32* %5, align 4

  store i32 6, i32* %6, align 4

; CHECK:                bl [[OUTLINED_FUNC:OUTLINED_FUNCTION_[0-9]+]]

; CHECK:                autibsp

; CHECK-NEXT:           ret

  ret void

}



define void @c() "sign-return-address"="all" "sign-return-address-key"="b_key" nounwind {

; CHECK-LABEL:      c:                                     // @c

; CHECK-NEXT:       // %bb.0:

; CHECK-NEXT:           pacibsp

  %1 = alloca i32, align 4

  %2 = alloca i32, align 4

  %3 = alloca i32, align 4

  %4 = alloca i32, align 4

  %5 = alloca i32, align 4

  %6 = alloca i32, align 4

  store i32 1, i32* %1, align 4

  store i32 2, i32* %2, align 4

  store i32 3, i32* %3, align 4

  store i32 4, i32* %4, align 4

  store i32 5, i32* %5, align 4

  store i32 6, i32* %6, align 4

; CHECK:                bl [[OUTLINED_FUNC]]

; CHECK:                autibsp

; CHECK-NEXT:           ret

  ret void

}



; CHECK:            [[OUTLINED_FUNC]]

; CHECK:            // %bb.0:

; CHECK-NEXT:           .cfi_b_key_frame

; CHECK-NEXT:           pacibsp

; CHECK-NEXT:           .cfi_negate_ra_state

; CHECK:                autibsp

; CHECK-NEXT:           ret

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll

0 → 100644
+68 −0
Original line number Diff line number Diff line 
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \

; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s



define void @a() "sign-return-address"="all" {

; CHECK-LABEL:      a:                                     // @a

; CHECK:            paciasp

; CHECK-NEXT:       .cfi_negate_ra_state

  %1 = alloca i32, align 4

  %2 = alloca i32, align 4

  %3 = alloca i32, align 4

  %4 = alloca i32, align 4

  %5 = alloca i32, align 4

  %6 = alloca i32, align 4

  store i32 1, i32* %1, align 4

  store i32 2, i32* %2, align 4

  store i32 3, i32* %3, align 4

  store i32 4, i32* %4, align 4

  store i32 5, i32* %5, align 4

  store i32 6, i32* %6, align 4

; CHECK:          autiasp

  ret void

; CHECK:          .cfi_endproc

}



define void @b() "sign-return-address"="non-leaf" {

; CHECK-LABEL:      b:                                     // @b

; CHECK-NOT:        paciasp

; CHECK-NOT:       .cfi_negate_ra_state

  %1 = alloca i32, align 4

  %2 = alloca i32, align 4

  %3 = alloca i32, align 4

  %4 = alloca i32, align 4

  %5 = alloca i32, align 4

  %6 = alloca i32, align 4

  store i32 1, i32* %1, align 4

  store i32 2, i32* %2, align 4

  store i32 3, i32* %3, align 4

  store i32 4, i32* %4, align 4

  store i32 5, i32* %5, align 4

  store i32 6, i32* %6, align 4

; CHECK-NOT:        autiasp

  ret void

; CHECK:            .cfi_endproc

}



define void @c() "sign-return-address"="all" {

; CHECK-LABEL:      c:                                     // @c

; CHECK:            paciasp

; CHECK-NEXT:       .cfi_negate_ra_state

  %1 = alloca i32, align 4

  %2 = alloca i32, align 4

  %3 = alloca i32, align 4

  %4 = alloca i32, align 4

  %5 = alloca i32, align 4

  %6 = alloca i32, align 4

  store i32 1, i32* %1, align 4

  store i32 2, i32* %2, align 4

  store i32 3, i32* %3, align 4

  store i32 4, i32* %4, align 4

  store i32 5, i32* %5, align 4

  store i32 6, i32* %6, align 4

; CHECK:          autiasp

  ret void

; CHECK:          .cfi_endproc

}



; CHECK-NOT:      OUTLINED_FUNCTION_{{[0-9]+}}:

; CHECK-NOT:      // -- Begin function

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll

0 → 100644
+72 −0
Original line number Diff line number Diff line 
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \

; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s



define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {

; CHECK-LABEL:      a:                                     // @a

; CHECK:                .cfi_b_key_frame

; CHECK-NEXT:           pacibsp

; CHECK-NEXT:           .cfi_negate_ra_state

  %1 = alloca i32, align 4

  %2 = alloca i32, align 4

  %3 = alloca i32, align 4

  %4 = alloca i32, align 4

  %5 = alloca i32, align 4

  %6 = alloca i32, align 4

  store i32 1, i32* %1, align 4

  store i32 2, i32* %2, align 4

  store i32 3, i32* %3, align 4

  store i32 4, i32* %4, align 4

  store i32 5, i32* %5, align 4

  store i32 6, i32* %6, align 4

  call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1

  ret i64 %x

}



define i64 @b(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {

; CHECK-LABEL:      b:                                     // @b

; CHECK:                .cfi_b_key_frame

; CHECK-NEXT:           pacibsp

; CHECK-NEXT:           .cfi_negate_ra_state

  %1 = alloca i32, align 4

  %2 = alloca i32, align 4

  %3 = alloca i32, align 4

  %4 = alloca i32, align 4

  %5 = alloca i32, align 4

  %6 = alloca i32, align 4

  store i32 1, i32* %1, align 4

  store i32 2, i32* %2, align 4

  store i32 3, i32* %3, align 4

  store i32 4, i32* %4, align 4

  store i32 5, i32* %5, align 4

  store i32 6, i32* %6, align 4

  call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1

  ret i64 %x

}



define i64 @c(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {

; CHECK-LABEL:      c:                                     // @c

; CHECK:                .cfi_b_key_frame

; CHECK-NEXT:           pacibsp

; CHECK-NEXT:           .cfi_negate_ra_state

  %1 = alloca i32, align 4

  %2 = alloca i32, align 4

  %3 = alloca i32, align 4

  %4 = alloca i32, align 4

  %5 = alloca i32, align 4

  %6 = alloca i32, align 4

  store i32 1, i32* %1, align 4

  store i32 2, i32* %2, align 4

  store i32 3, i32* %3, align 4

  store i32 4, i32* %4, align 4

  store i32 5, i32* %5, align 4

  store i32 6, i32* %6, align 4

  call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1

  ret i64 %x

}



; Outlined function is leaf-function => don't sign it

; CHECK-LABEL:      OUTLINED_FUNCTION_0:

; CHECK-NOT:            .cfi_b_key_frame

; CHECK-NOT:            paci{{[a,b]}}sp

; CHECK-NOT:            .cfi_negate_ra_state

; CHECK-NOT:            auti{{[a,b]}}sp

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir

0 → 100644
+127 −0

File added.

Preview size limit exceeded, changes collapsed.