Loading llvm/docs/ReleaseNotes.rst +14 −2 Original line number Diff line number Diff line Loading @@ -135,11 +135,23 @@ During this release the SystemZ target has: Changes to the X86 Target ------------------------- During this release ... During this release the X86 target has: * Got support for enabling SjLj exception handling on platforms where it * Added support for enabling SjLj exception handling on platforms where it isn't the default. * Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. * Added support for Intel Icelake CPU. * Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. * Improved codegen of data being transferred between GPRs and K-registers. * Improved llvm-mc's disassembler for some EVEX encoded instructions. * Improved codegen for vector truncations. Changes to the AMDGPU Target ----------------------------- Loading Loading
llvm/docs/ReleaseNotes.rst +14 −2 Original line number Diff line number Diff line Loading @@ -135,11 +135,23 @@ During this release the SystemZ target has: Changes to the X86 Target ------------------------- During this release ... During this release the X86 target has: * Got support for enabling SjLj exception handling on platforms where it * Added support for enabling SjLj exception handling on platforms where it isn't the default. * Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI. * Added support for Intel Icelake CPU. * Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. * Improved codegen of data being transferred between GPRs and K-registers. * Improved llvm-mc's disassembler for some EVEX encoded instructions. * Improved codegen for vector truncations. Changes to the AMDGPU Target ----------------------------- Loading
