Commit dcceab1a authored by Stefan Pintilie's avatar Stefan Pintilie
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[PowerPC] Add new Future CPU for PowerPC in LLVM 

This is a continuation of D70262
The previous patch as listed above added the future CPU in clang. This patch
adds the future CPU in the PowerPC backend. At this point the patch simply
assumes that a future CPU will have the same characteristics as pwr9. Those
characteristics may change with later patches.

Differential Revision: https://reviews.llvm.org/D70333
parent f584f04d

llvm/lib/Support/Host.cpp

+3 −0
Original line number Diff line number Diff line
@@ -140,6 +140,9 @@ StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 
      .Case("POWER8E", "pwr8")

      .Case("POWER8NVL", "pwr8")

      .Case("POWER9", "pwr9")

      // FIXME: If we get a simulator or machine with the capabilities of

      // mcpu=future, we should revisit this and add the name reported by the

      // simulator/machine.

      .Default(generic);

}

llvm/lib/Target/PowerPC/PPC.td

+12 −0
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ def DirectivePwr6x 
def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;

def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;

def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;

def DirectivePwrFuture

    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;



def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",

                                        "Enable 64-bit instructions">;
@@ -239,6 +241,13 @@ def ProcessorFeatures { 
       FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched];

  list<SubtargetFeature> Power9FeatureList =

      !listconcat(Power8FeatureList, Power9SpecificFeatures);



  // For future CPU we assume that all of the existing features from Power 9

  // still exist.

  list<SubtargetFeature> FutureSpecificFeatures =

      [];

  list<SubtargetFeature> FutureFeatureList =

      !listconcat(Power9FeatureList, FutureSpecificFeatures);

}



// Note: Future features to add when support is extended to more
@@ -441,6 +450,9 @@ def : ProcessorModel<"pwr6x", G5Model, 
def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;

def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;

def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>;

// No scheduler model for future CPU.

def : ProcessorModel<"future", NoSchedModel,

                  ProcessorFeatures.FutureFeatureList>;

def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,

                                       FeatureMFTB]>;

def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

+2 −1
Original line number Diff line number Diff line
@@ -1603,7 +1603,8 @@ void PPCDarwinAsmPrinter::EmitStartOfAsmFile(Module &M) { 
    // FIXME: why is power8 missing here?

    "ppc64",

    "ppc64le",

    "power9"

    "power9",

    "future"

  };



  // Get the numerically largest directive.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

+4 −1
Original line number Diff line number Diff line
@@ -1217,6 +1217,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, 
  case PPC::DIR_PWR7:

  case PPC::DIR_PWR8:

  case PPC::DIR_PWR9:

  case PPC::DIR_PWR_FUTURE:

    setPrefLoopAlignment(Align(16));

    setPrefFunctionAlignment(Align(16));

    break;
@@ -14204,7 +14205,8 @@ Align PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const { 
  case PPC::DIR_PWR6X:

  case PPC::DIR_PWR7:

  case PPC::DIR_PWR8:

  case PPC::DIR_PWR9: {

  case PPC::DIR_PWR9:

  case PPC::DIR_PWR_FUTURE: {

    if (!ML)

      break;










@@ -15383,6 +15385,7 @@ SDValue PPCTargetLowering::combineMUL(SDNode *N, DAGCombinerInfo &DCI) const {













      // vector        7       2      2















      return true;















    case PPC::DIR_PWR9:













    case PPC::DIR_PWR_FUTURE:















      //  type        mul     add    shl















      // scalar        5       2      2















      // vector        7       2      2

























llvm/lib/Target/PowerPC/PPCSubtarget.h



+1
−0






























Original line number
Diff line number
Diff line








@@ -57,6 +57,7 @@ namespace PPC {













    DIR_PWR7,















    DIR_PWR8,















    DIR_PWR9,













    DIR_PWR_FUTURE,















    DIR_64















  };















}