Commit d65c3bf3 authored by Hassnaa Hamdi's avatar Hassnaa Hamdi
Browse files

[AArch64][CostModel]: Add costs for zero/sign extend. 

Add cost for extending to illegal scalable vector types.
Add testing file for the extend operations.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D142456
parent 02d84892

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

+17 −0
Original line number Diff line number Diff line
@@ -2072,6 +2072,23 @@ InstructionCost AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 
    { ISD::BITCAST, MVT::nxv2i16, MVT::nxv2f16, 0 },

    { ISD::BITCAST, MVT::nxv4i16, MVT::nxv4f16, 0 },

    { ISD::BITCAST, MVT::nxv2i32, MVT::nxv2f32, 0 },



    // Add cost for extending to illegal -too wide- scalable vectors.

    // zero/sign extend are implemented by multiple unpack operations,

    // where each operation has a cost of 1.

    { ISD::ZERO_EXTEND, MVT::nxv16i16, MVT::nxv16i8, 2},

    { ISD::ZERO_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 6},

    { ISD::ZERO_EXTEND, MVT::nxv16i64, MVT::nxv16i8, 14},

    { ISD::ZERO_EXTEND, MVT::nxv8i32, MVT::nxv8i16, 2},

    { ISD::ZERO_EXTEND, MVT::nxv8i64, MVT::nxv8i16, 6},

    { ISD::ZERO_EXTEND, MVT::nxv4i64, MVT::nxv4i32, 2},



    { ISD::SIGN_EXTEND, MVT::nxv16i16, MVT::nxv16i8, 2},

    { ISD::SIGN_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 6},

    { ISD::SIGN_EXTEND, MVT::nxv16i64, MVT::nxv16i8, 14},

    { ISD::SIGN_EXTEND, MVT::nxv8i32, MVT::nxv8i16, 2},

    { ISD::SIGN_EXTEND, MVT::nxv8i64, MVT::nxv8i16, 6},

    { ISD::SIGN_EXTEND, MVT::nxv4i64, MVT::nxv4i32, 2},

  };



  if (const auto *Entry = ConvertCostTableLookup(ConversionTbl, ISD,

llvm/test/Analysis/CostModel/AArch64/cast.ll

+2 −2
Original line number Diff line number Diff line
@@ -858,8 +858,8 @@ define i32 @load_extends() #0 { 
; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v13 = zext <4 x i32> %loadv4i32 to <4 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v14 = sext <vscale x 2 x i32> %loadnxv2i32 to <vscale x 2 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v15 = zext <vscale x 2 x i32> %loadnxv2i32 to <vscale x 2 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16 = sext <vscale x 4 x i32> %loadnxv4i32 to <vscale x 4 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v17 = zext <vscale x 4 x i32> %loadnxv4i32 to <vscale x 4 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v16 = sext <vscale x 4 x i32> %loadnxv4i32 to <vscale x 4 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v17 = zext <vscale x 4 x i32> %loadnxv4i32 to <vscale x 4 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef

;

  %loadi8 = load i8, ptr undef

llvm/test/Analysis/CostModel/AArch64/sve-ext.ll

0 → 100644
+37 −0
Original line number Diff line number Diff line 
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py

; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple aarch64-linux-gnu -mattr=+sve -S -o - < %s | FileCheck %s



target triple = "aarch64-unknown-linux-gnu"



define void @sve_ext() {

; CHECK-LABEL: 'sve_ext'

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %zext_nxv16_i8_to_i16 = zext <vscale x 16 x i8> undef to <vscale x 16 x i16>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %zext_nxv16_i8_to_i32 = zext <vscale x 16 x i8> undef to <vscale x 16 x i32>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %zext_nxv16_i8_to_i64 = zext <vscale x 16 x i8> undef to <vscale x 16 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %zext_nxv8_i16_to_i32 = zext <vscale x 8 x i16> undef to <vscale x 8 x i32>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %zext_nxv8_i16_to_i64 = zext <vscale x 8 x i16> undef to <vscale x 8 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %zext_nxv4_i32_to_i64 = zext <vscale x 4 x i32> undef to <vscale x 4 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sext_nxv16_i8_to_i16 = sext <vscale x 16 x i8> undef to <vscale x 16 x i16>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %sext_nxv16_i8_to_i32 = sext <vscale x 16 x i8> undef to <vscale x 16 x i32>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %sext_nxv16_i8_to_i64 = sext <vscale x 16 x i8> undef to <vscale x 16 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sext_nxv8_i16_to_i32 = sext <vscale x 8 x i16> undef to <vscale x 8 x i32>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %sext_nxv8_i16_to_i64 = sext <vscale x 8 x i16> undef to <vscale x 8 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sext_nxv4_i32_to_i64 = sext <vscale x 4 x i32> undef to <vscale x 4 x i64>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void

;

  %zext_nxv16_i8_to_i16 = zext <vscale x 16 x i8> undef to <vscale x 16 x i16>

  %zext_nxv16_i8_to_i32 = zext <vscale x 16 x i8> undef to <vscale x 16 x i32>

  %zext_nxv16_i8_to_i64 = zext <vscale x 16 x i8> undef to <vscale x 16 x i64>

  %zext_nxv8_i16_to_i32 = zext <vscale x 8 x i16> undef to <vscale x 8 x i32>

  %zext_nxv8_i16_to_i64 = zext <vscale x 8 x i16> undef to <vscale x 8 x i64>

  %zext_nxv4_i32_to_i64 = zext <vscale x 4 x i32> undef to <vscale x 4 x i64>



  %sext_nxv16_i8_to_i16 = sext <vscale x 16 x i8> undef to <vscale x 16 x i16>

  %sext_nxv16_i8_to_i32 = sext <vscale x 16 x i8> undef to <vscale x 16 x i32>

  %sext_nxv16_i8_to_i64 = sext <vscale x 16 x i8> undef to <vscale x 16 x i64>

  %sext_nxv8_i16_to_i32 = sext <vscale x 8 x i16> undef to <vscale x 8 x i32>

  %sext_nxv8_i16_to_i64 = sext <vscale x 8 x i16> undef to <vscale x 8 x i64>

  %sext_nxv4_i32_to_i64 = sext <vscale x 4 x i32> undef to <vscale x 4 x i64>



  ret void

}

llvm/test/Analysis/CostModel/AArch64/sve-widening-instruction.ll

+2 −2
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@@ -20,8 +20,8 @@ define <vscale x 4 x i32> @widening_nxv4i16(<vscale x 4 x i16> %in1, <vscale x 4 


define <vscale x 8 x i32> @widening_nxv8i16(<vscale x 8 x i16> %in1, <vscale x 8 x i16> %in2) {

; CHECK-LABEL: 'widening_nxv8i16'

; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %in1.ext = zext <vscale x 8 x i16> %in2 to <vscale x 8 x i32>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %in2.ext = zext <vscale x 8 x i16> %in2 to <vscale x 8 x i32>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %in1.ext = zext <vscale x 8 x i16> %in2 to <vscale x 8 x i32>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %in2.ext = zext <vscale x 8 x i16> %in2 to <vscale x 8 x i32>

; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %in.add = add <vscale x 8 x i32> %in1.ext, %in2.ext

; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <vscale x 8 x i32> %in.add

;