Commit d2647fa6 authored by Hans Wennborg's avatar Hans Wennborg
Browse files

Merging r341512: 

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r341512 | ctopper | 2018-09-06 04:03:14 +0200 (Thu, 06 Sep 2018) | 7 lines

[X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives.

This basically reverts a change made in r336217, but improves the text of the error message for not allowing IP-relative addressing in 32-bit mode.

Fixes PR38826.

Patch by Iain Sandoe.
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llvm-svn: 341530
parent f1c57fe8

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

+2 −2
Original line number Diff line number Diff line
@@ -1054,7 +1054,7 @@ static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, 
  // RIP/EIP-relative addressing is only supported in 64-bit mode.

  if (!Is64BitMode && BaseReg != 0 &&

      (BaseReg == X86::RIP || BaseReg == X86::EIP)) {

    ErrMsg = "RIP-relative addressing requires 64-bit mode";

    ErrMsg = "IP-relative addressing requires 64-bit mode";

    return true;

  }
@@ -1099,7 +1099,7 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo, 
    // checked.

    // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a

    // REX prefix.

    if (RegNo == X86::RIZ || RegNo == X86::RIP || RegNo == X86::EIP ||

    if (RegNo == X86::RIZ || RegNo == X86::RIP ||

        X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||

        X86II::isX86_64NonExtLowByteReg(RegNo) ||

        X86II::isX86_64ExtendedReg(RegNo))

llvm/test/CodeGen/X86/eip-addressing-i386.ll

+2 −2
Original line number Diff line number Diff line 
; RUN: not llc -mtriple i386-apple-- -o /dev/null < %s 2>&1| FileCheck %s

; CHECK: <inline asm>:1:13: error: register %eip is only available in 64-bit mode

; CHECK: <inline asm>:1:13: error: IP-relative addressing requires 64-bit mode

; CHECK-NEXT: jmpl *_foo(%eip)



; Make sure that we emit an error if we encounter RIP-relative instructions in

; Make sure that we emit an error if we encounter IP-relative instructions in

; 32-bit mode.



define i32 @foo() { ret i32 0 }

llvm/test/MC/X86/pr38826.s

0 → 100644
+24 −0
Original line number Diff line number Diff line 
// RUN: llvm-mc %s -triple i386-unknown-unknown



// Make sure %eip is allowed as a register in cfi directives in 32-bit mode



 .text

 .align 4

 .globl foo



foo:

 .cfi_startproc



 movl (%edx), %ecx

 movl 4(%edx), %ebx

 movl 8(%edx), %esi

 movl 12(%edx), %edi

 movl 16(%edx), %ebp

 .cfi_def_cfa %edx, 0

 .cfi_offset %eip, 24

 .cfi_register %esp, %ecx

 movl %ecx, %esp



 jmp *24(%edx)



 .cfi_endproc

llvm/test/MC/X86/x86_errors.s

+2 −2
Original line number Diff line number Diff line
@@ -103,11 +103,11 @@ lea (%si,%bx), %ax 
// 64: error: invalid 16-bit base register

lea (%di,%bx), %ax



// 32: error: register %eip is only available in 64-bit mode

// 32: error: invalid base+index expression

// 64: error: invalid base+index expression

mov (,%eip), %rbx



// 32: error: register %eip is only available in 64-bit mode

// 32: error: invalid base+index expression

// 64: error: invalid base+index expression

mov (%eip,%eax), %rbx