Loading llvm/lib/Target/RISCV/RISCVISelLowering.cpp +2 −0 Original line number Diff line number Diff line Loading @@ -6452,6 +6452,8 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, case RISCVISD::READ_VLENB: // We assume VLENB is at least 16 bytes. Known.Zero.setLowBits(4); // We assume VLENB is no more than 65536 / 8 bytes. Known.Zero.setBitsFrom(14); break; case ISD::INTRINSIC_W_CHAIN: { unsigned IntNo = Op.getConstantOperandVal(1); Loading llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll +3 −3 Original line number Diff line number Diff line Loading @@ -50,9 +50,9 @@ define i64 @vscale_uimmpow2xlen() nounwind { ; ; RV32-LABEL: vscale_uimmpow2xlen: ; RV32: # %bb.0: # %entry ; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: slli a0, a1, 3 ; RV32-NEXT: srli a1, a1, 29 ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: mv a1, zero ; RV32-NEXT: ret entry: %0 = call i64 @llvm.vscale.i64() Loading Loading
llvm/lib/Target/RISCV/RISCVISelLowering.cpp +2 −0 Original line number Diff line number Diff line Loading @@ -6452,6 +6452,8 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, case RISCVISD::READ_VLENB: // We assume VLENB is at least 16 bytes. Known.Zero.setLowBits(4); // We assume VLENB is no more than 65536 / 8 bytes. Known.Zero.setBitsFrom(14); break; case ISD::INTRINSIC_W_CHAIN: { unsigned IntNo = Op.getConstantOperandVal(1); Loading
llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll +3 −3 Original line number Diff line number Diff line Loading @@ -50,9 +50,9 @@ define i64 @vscale_uimmpow2xlen() nounwind { ; ; RV32-LABEL: vscale_uimmpow2xlen: ; RV32: # %bb.0: # %entry ; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: slli a0, a1, 3 ; RV32-NEXT: srli a1, a1, 29 ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: mv a1, zero ; RV32-NEXT: ret entry: %0 = call i64 @llvm.vscale.i64() Loading