Commit cf874a21 authored by Pawel Bylica's avatar Pawel Bylica
Browse files

Merging r286998: 

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r286998 | chfast | 2016-11-15 19:29:24 +0100 (wto, 15 lis 2016) | 12 lines

Integer legalization: fix MUL expansion

Summary:
This fixes the runtime results produces by the fallback multiplication expansion introduced in r270720.

For tests I created a fuzz tester that compares the results with Boost.Multiprecision.

Reviewers: hfinkel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26628

llvm-svn: 288086
parent 97214e4f

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

+4 −4
Original line number Diff line number Diff line
@@ -2207,7 +2207,7 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 
    SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);



    SDValue U = DAG.getNode(ISD::ADD, dl, NVT,

                            DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TL);

                            DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);

    SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);

    SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
@@ -2216,9 +2216,9 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 
    SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);



    SDValue W = DAG.getNode(ISD::ADD, dl, NVT,

                            DAG.getNode(ISD::MUL, dl, NVT, LL, RL),

                            DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),

                            DAG.getNode(ISD::ADD, dl, NVT, UH, VH));

    Lo = DAG.getNode(ISD::ADD, dl, NVT, TH,

    Lo = DAG.getNode(ISD::ADD, dl, NVT, TL,

                     DAG.getNode(ISD::SHL, dl, NVT, V, Shift));



    Hi = DAG.getNode(ISD::ADD, dl, NVT, W,

llvm/test/CodeGen/X86/mul-i1024.ll

+3909 −3427

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llvm/test/CodeGen/X86/mul-i256.ll

+7 −2
Original line number Diff line number Diff line
@@ -15,12 +15,17 @@ entry: 
; There is a lot of inter-register motion, and so matching the instruction

; sequence will be fragile. There should be 6 underlying multiplications.

; CHECK: imulq

; CHECK: mulq

; CHECK: imulq

; CHECK: imulq

; CHECK: mulq

; CHECK: imulq

; CHECK: imulq

; CHECK: imulq

; CHECK: mulq

; CHECK: mulq

; CHECK: mulq

; CHECK: mulq

; CHECK-NOT: imulq

; CHECK-NOT: mulq

; CHECK: retq



attributes #0 = { norecurse nounwind uwtable "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" }

llvm/test/CodeGen/X86/mul-i512.ll

+722 −687

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