Commit c7be0679 authored by Yi-Hong Lyu's avatar Yi-Hong Lyu
Browse files

[PowerPC] Fix SH field overflow issue 

Store rlwinm Rx, Ry, 32, 0, 31 as rlwinm Rx, Ry, 0, 0, 31 and store
rldicl Rx, Ry, 64, 0 as rldicl Rx, Ry, 0, 0. Otherwise SH field is overflow and
fails assertion in assembly printing stage.

Differential Revision: https://reviews.llvm.org/D66991

llvm-svn: 373519
parent e55c442b

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

+8 −4
Original line number Diff line number Diff line
@@ -3571,16 +3571,20 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI, 
      } else {

        // The 32 bit and 64 bit instructions are quite different.

        if (SpecialShift32) {

          // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).

          uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;

          // Left shifts use (N, 0, 31-N).

          // Right shifts use (32-N, N, 31) if 0 < N < 32.

          //              use (0, 0, 31)    if N == 0.

          uint64_t SH = ShAmt == 0 ? 0 : RightShift ? 32 - ShAmt : ShAmt;

          uint64_t MB = RightShift ? ShAmt : 0;

          uint64_t ME = RightShift ? 31 : 31 - ShAmt;

          replaceInstrOperandWithImm(MI, III.OpNoForForwarding, SH);

          MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)

            .addImm(ME);

        } else {

          // Left shifts use (N, 63-N), right shifts use (64-N, N).

          uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;

          // Left shifts use (N, 63-N).

          // Right shifts use (64-N, N) if 0 < N < 64.

          //              use (0, 0)    if N == 0.

          uint64_t SH = ShAmt == 0 ? 0 : RightShift ? 64 - ShAmt : ShAmt;

          uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;

          replaceInstrOperandWithImm(MI, III.OpNoForForwarding, SH);

          MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);

llvm/test/CodeGen/PowerPC/sh-overflow.mir

0 → 100644
+58 −0
Original line number Diff line number Diff line 
# RUN: llc -O3 -mtriple=powerpc64le-unknown-linux-gnu -start-after ppc-mi-peepholes -ppc-late-peephole -ppc-asm-full-reg-names -verify-machineinstrs %s -o - | FileCheck %s



---

name:            special_right_shift32_0

alignment:       2

tracksRegLiveness: true

registers:

  - { id: 0, class: gprc }

  - { id: 1, class: gprc }

  - { id: 2, class: gprc }

liveins:

  - { reg: '$r3', virtual-reg: '%0' }

machineFunctionInfo: {}

body:             |

  bb.0.entry:

    liveins: $r3



    ; Ensure we do not attempt to transform this into srwi $r3, $r3, 0 in the

    ; form specified by ISA 3.0b (rlwinm $r3, $r3, 32 - 0, 0, 31)



    ; CHECK-LABEL: special_right_shift32_0:

    ; CHECK:         slwi r[[#]], r[[#]], 0



    %0:gprc = COPY killed $r3

    %1:gprc = LI 0

    %2:gprc = SRW killed %0, killed %1

    $r3 = COPY killed %2

    BLR implicit $lr, implicit $rm, implicit killed $r3



...

---

name:            special_right_shift64_0

alignment:       2

tracksRegLiveness: true

registers:

  - { id: 0, class: g8rc }

  - { id: 1, class: gprc }

  - { id: 2, class: g8rc }

liveins:

  - { reg: '$x3', virtual-reg: '%0' }

machineFunctionInfo: {}

body:             |

  bb.0.entry:

    liveins: $x3



    ; Ensure we do not attempt to transform this into srdi $r3, $r3, 0 in the

    ; form specified by ISA 3.0b (rldicl $r3, $r3, 64 - 0, 0)



    ; CHECK-LABEL: special_right_shift64_0:

    ; CHECK:         rotldi r[[#]], r[[#]], 0



    %0:g8rc = COPY killed $x3

    %1:gprc = LI 0

    %2:g8rc = SRD killed %0, killed %1

    $x3 = COPY killed %2

    BLR8 implicit $lr8, implicit $rm, implicit killed $x3



...